Impact of Through-Silicon-Via capacitance on high frequency supply noise in 3D-stacks

Trivedi, Amit Ranjan; Yueh, Wen; Mukhopadhyay, Saibal

doi:10.1109/epeps.2011.6100199

Cited by 8 publications

(5 citation statements)

References 7 publications

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“…As shown in Fig 1, Typically PIG TSVs are made bigger to minimize electro migration and reliability issues. Their larger sizes also means they have significant capacitance which can act as extra on chip distributed decap, reducing high frequency dildt noise [5]. Even at lower frequency the increase of effective inductance (due to the reduction in number of power pins) is countered by dampening effect provided by increase of resistance.…”

Section: A Power Delivery Modelmentioning

confidence: 99%

Breaking the 3D IC power delivery wall

Mazumdar

Stan

2012

2012 Conference Record of the Forty Sixth Asilomar Conference on Signals, Systems and Computers (ASILOMAR)

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Several power "walls" that must be overcome in future technologies are the 3D IC power delivery wall and the on chip power regulation efficiency wall. In 3D ICs, power is consumed in the volume of the 3D chip, but can be delivered only to a 2D surface -as the number of layers in a 3D IC becomes larger, the greater the mismatch between 3D consumption and 2D delivery. The efficiency of on-chip regulators, which bounds the overall power efficiency of an IC, is not unique to 3D, but becomes essential due to the volumetric nature of the system. This paper studies voltage stacking of multi-layer heterogeneous 3D systems with distributed DC-to-DC on-chip regulators. The physical layering of 3D IC naturally maps to a voltage stacked solution that overcomes some of the difficulties with voltage stacking in 2D, such as isolating the stacked domains from the substrate. The paper presents a design methodology and optimization strategy for efficient on chip regulation using switch capacitor. Through simulation, we show how voltage stacked clustered layers can help overcome some of the limitations in 3D IC power delivery design.

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Section: A Power Delivery Modelmentioning

confidence: 99%

Breaking the 3D IC power delivery wall

Mazumdar

Stan

2012

2012 Conference Record of the Forty Sixth Asilomar Conference on Signals, Systems and Computers (ASILOMAR)

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“…The main difference between the proposed model and previous models [6]- [13] that the ground plane is approximated by the cell placing areas and the proposed model is simplified by the small ground area surrounding each TSV. Fig.…”

Section: B Electrical Model Of Tsv-to-tsv Coupling With Substratementioning

confidence: 99%

“…Especially, in designs with bulk CMOS technologies, many substrate contacts are used to avoid latch-up and to maintain back-gate bias constantly. Some circuit models that consider these substrate contacts have been proposed [6]- [13]. Most of them focused on the substrate noise and presented modeling and analysis results for substrate noise coupling in analog, RF, and digital circuits.…”

Section: Introductionmentioning

confidence: 99%

Effect of substrate contacts on reducing crosstalk noise between TSVs

Watanabe

Karel

Niioka

et al. 2014

2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

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We propose a model for coupling that considers substrate contacts between through silicon vias (TSVs) in bulk-CMOS technologies. The proposed model is compact but has reasonable accuracy for the dense substrate contacts in largescale three dimensional integrated circuits (3D ICs). We describe the modeling for substrate contacts with the equivalent electrical circuit, discuss the impact of substrate contacts on the electrical parasitic parameters, and clarify the effect of substrate contacts on reducing crosstalk noise and increasing delay. Results of analysis show that if substrate contacts are not considered, crosstalk noise becomes the overestimate of 5 to 700 times and delay becomes the underestimate of 1.4 to 2.4 times.

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“…The corresponding TSV resistances and capacitances are extracted from 3-D TCAD simulation. The TCAD simulation accurately accounts for the MOS capacitance of the P/G TSVs as described in our earlier work [20], [24]. The TSV inductance is referenced from the work of Katti et al [25].…”

Section: B Supply Modeling With a 3-d Rlc Power Gridmentioning

confidence: 99%

Performance and Robustness of 3-D Integrated SRAM Considering Tier-to-Tier Thermal and Supply Crosstalk

Yueh

Chatterjee

Trivedi

et al. 2013

IEEE Trans. Compon., Packag. Manufact. Technol.

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This paper analyzes the effect of tier-to-tier thermal and supply crosstalk on the performance and robustness of the static random access memory (SRAM) within a 3-D stack under crosstalk influence of the logic cores. Our framework integrates distributed process variation aware circuit analysis, RC-based thermal simulation, and distributed RLC-based power delivery network simulation. The analysis shows when the logic cores and SRAMs are integrated in 3-D stack, the thermal and supply crosstalk degrade the SRAM performance and noise margin during read and write operations.Index Terms-Die-to-die thermal and supply crosstalk, hotspots, power delivery network (PDN), robustness, static random access memory (SRAM), supply noise, through silicon via (TSV), 3-D core-memory stack, 3-D integration.

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Impact of Through-Silicon-Via capacitance on high frequency supply noise in 3D-stacks

Cited by 8 publications

References 7 publications

Breaking the 3D IC power delivery wall

Breaking the 3D IC power delivery wall

Effect of substrate contacts on reducing crosstalk noise between TSVs

Performance and Robustness of 3-D Integrated SRAM Considering Tier-to-Tier Thermal and Supply Crosstalk

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