Impact of Variation in Barrier Thickness on a Gate-Engineered TM-DG Heterostructure MOSFET to Suppress SCE's and it's Analog, RF, Linearity Performance Investigation for SOC Applications

Baral, Biswajit; Biswal, Sudhansu Mohan; Priya, P. Hari; Pani, Sarita; Swain, Sanjit Kumar

doi:10.1109/edkcon.2018.8770475

2018 IEEE Electron Devices Kolkata Conference (EDKCON) 2018

DOI: 10.1109/edkcon.2018.8770475

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Impact of Variation in Barrier Thickness on a Gate-Engineered TM-DG Heterostructure MOSFET to Suppress SCE's and it's Analog, RF, Linearity Performance Investigation for SOC Applications

Biswajit Baral¹,

Sudhansu Mohan Biswal²,

P. Hari Priya³

et al.

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2024

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Optimized Gate Metal Variant Structure for Graded-Channel (GC) Gate-Stack (GS) Double-Gate (DG) MOSFET to Enhance Switching Speed, Analog and RF Performance

Chowdhury,

DasMahapatra,

et al. 2024

J. Electron. Mater.

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Optimized Gate Metal Variant Structure for Graded-Channel (GC) Gate-Stack (GS) Double-Gate (DG) MOSFET to Enhance Switching Speed, Analog and RF Performance

Chowdhury,

DasMahapatra,

et al. 2024

J. Electron. Mater.

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Impact of Variation in Barrier Thickness on a Gate-Engineered TM-DG Heterostructure MOSFET to Suppress SCE's and it's Analog, RF, Linearity Performance Investigation for SOC Applications

Cited by 1 publication

References 6 publications

Optimized Gate Metal Variant Structure for Graded-Channel (GC) Gate-Stack (GS) Double-Gate (DG) MOSFET to Enhance Switching Speed, Analog and RF Performance

Optimized Gate Metal Variant Structure for Graded-Channel (GC) Gate-Stack (GS) Double-Gate (DG) MOSFET to Enhance Switching Speed, Analog and RF Performance

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