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The analog/radio frequency (RF) and linearity performance of a junctionless double gate metal-oxide-semiconductor field-effect transistor (JL DGMOS) is investigated using the numerical TCAD device simulator. JL DGMOSs have shown great promise for high-performance digital applications due to their superior short channel effect performance and ease of fabrication. In analog and RF circuit applications, linearity testing and RF performance is a major issue that is encountered due to non-linear behavior of the devices. Therefore, in this paper, different RF/analog and linearity performance figures of merits such as transconductance, intrinsic gain, the transconductance generation factor, the cut off frequency, the maximum frequency of oscillation, the gain bandwidth product, the variable intercept point of second order, the variable intercept point of third order, inter modulation distortion, the third-order intercept point, and 1-dB compression have been presented. Moreover, the effect of gate-length downscaling on these performance parameters has been carried out. The results indicate that the down scaled JL DGMOS shows great promise to become a competitive contender for analog/mixed signal system on chip applications by demonstrating a significant improvement in its RF performance with gate-length downscaling.

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Summary In this paper, the analog/radio frequency (RF) and linearity performance of an InAs‐based nanowire (NW) tunnel field‐effect transistor (TFET) is studied and compared with InAs‐based NW MSFET of identical dimension. InAs‐based NW TFETs shows a great promise for high performance digital application because of its superior subthreshold behavior. Different analog/RF and linearity key figure‐of‐merits like cut‐off frequency (ft) and 1‐dB compression point are extracted and the effect of gate length down scaling on those parameters has been studied. The results reveal that down scaled InAs‐based NW TFET shows a significant improvement in its RF and linearity performance. However, this advantage diminishes in terms of poor analog performance with gate‐length downscaling. This clearly indicates the necessity of a trade‐off between analog and RF performance. Moreover, an in‐depth comparison between InAs‐based NW TFET and conventional MOSFET has also been provided in order to demonstrate the superiority of InAs‐based NW TFET to become a competitive contender by replacing conventional MOSFET for Analog/Mixed signal System‐on‐Chip (SOC) applications. Copyright © 2016 John Wiley & Sons, Ltd.

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