2016
DOI: 10.1016/j.spmi.2016.01.021
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Study of effect of gate-length downscaling on the analog/RF performance and linearity investigation of InAs-based nanowire Tunnel FET

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Cited by 46 publications
(15 citation statements)
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“…Several papers using a semi-classical approach to describe trap assisted tunneling by using a modified Shockley-Read-Hall formula found that traps can produce a sizable degradation of the SS, and investigated the minimum trap densities necessary for a steep slope behavior [51,120,[139][140][141]. In very recent references, for instance, it has been argued that the trap density should be decreased by 100 times with respect to the state of the art values in order to obtain IIIV TFETs with an SS below 60 mV/dec at room temperature [142].…”
Section: Effects Of Non-ideal Interfaces Defects and Trapsmentioning
confidence: 99%
“…Several papers using a semi-classical approach to describe trap assisted tunneling by using a modified Shockley-Read-Hall formula found that traps can produce a sizable degradation of the SS, and investigated the minimum trap densities necessary for a steep slope behavior [51,120,[139][140][141]. In very recent references, for instance, it has been argued that the trap density should be decreased by 100 times with respect to the state of the art values in order to obtain IIIV TFETs with an SS below 60 mV/dec at room temperature [142].…”
Section: Effects Of Non-ideal Interfaces Defects and Trapsmentioning
confidence: 99%
“…One of the most important approaches is to design and simulate analytical nanostructures. Many significant devices can be designed using this simulation procedure and analyze the obtained results [ 47 , 55 , 56 ]. According to the result, the researchers can modify the various simulation parameters as well as the different aspects of the nanoscale analytical model.…”
Section: Molecular-level Research Work Based On Electrical Dopingmentioning
confidence: 99%
“…It is evident that for channel length equal to10 nm better distortion suppression is acquired. IIP 3 is other important FOM that evaluates the linearity performance and is given by the following [27][28][29] :…”
Section: Impact Of Gate-length Downscaling On Linearity Performance Pmentioning
confidence: 99%
“…Linearity is directly proportional to transconductance and is inversely proportional to the second derivative of the transconductance. 27 It signifies that the devices with constant transconductance versus gate voltage curves, and trifling disparity across a particular voltage range, are more linear. In the following analysis of linearity for a JL DGMOS, g m 1 , g m 2 , and g m 3 are given by the following:…”
Section: Impact Of Gate-length Downscaling On Linearity Performancmentioning
confidence: 99%
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