Analytical subthreshold modeling of dual material gate engineered nano-scale junctionless surrounding gate MOSFET considering ECPE

Biswal, Sudhansu Mohan; Baral, Biswajit; De, Debashis; Sarkar, Angsuman

doi:10.1016/j.spmi.2015.02.018

Cited by 28 publications

(3 citation statements)

References 18 publications

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“…One major well-known and thoroughly investigated drawback of FET devices is short-channel effect [26][27][28] which leads to invention of several new architectures [29][30][31][32][33][34][35] including junctionless devices [36,37]. A perfect blend of junctionless device with dual material double gate (DMDG) architecture leads to lowering of subthreshold swing, optimizing DIBL, roll off of threshold as well improvement of ON-to-OFF current ratio [38]. Improvisation of these two novel concepts leads to formation of asymmetric junctionless DMDG device [39] as the most promising architecture based on electrical performance, though biomolecule detection has yet to be documented.…”

Section: Introductionmentioning

confidence: 99%

2D analytical modelling of asymmetric junctionless dual material double gate MOSFET for biosensing applications considering steric hindrance issue

Basak

Deyasi²,

Sarkar

2023

Phys. Scr.

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Improved sensitivity for both threshold voltage and ON-current has been reported in the present manuscript for Asymmetric Junctionless Dual Material Double Gate MOSFET (AJDMDG MOSFET) biosensor. The device has been constructed with both neutral and charged biomolecules in presence of high-K dielectric material. Threshold voltage is evaluated after computing minimum surface potential by solving 2D Poisson’s equation with parabolic-potential configuration subject to realistic boundary conditions. Analytical findings exhibit excellent agreement with TCAD simulation, which leads to an investigation of threshold voltage sensitivity with front-gate voltage having all feasible dimensional variations. Corresponding drain current sensitivity with a higher ON-to-OFF current ratio is theoretically estimated and compared with identical DGFET architecture, leading to significant improvement for all possible step patterns considering the steric hinderance issue for moderately filled cavities; which helps in detecting both labelled and label-free electrical species at lower concentration levels. 

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Section: Introductionmentioning

confidence: 99%

2D analytical modelling of asymmetric junctionless dual material double gate MOSFET for biosensing applications considering steric hindrance issue

Basak

Deyasi²,

Sarkar

2023

Phys. Scr.

Self Cite

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“…Device miniaturization in Complementary-Metal Oxide Semiconductor (CMOS) solid-state technologies in terms of gate length has been the vital concern for the researchers to abide Moore's law [1][2]. Bottle-necks such as short-channeleffects (SCEs), OFF-state current efflux, static-power dissipation as well as source and drain junctions are major concerns that needs to be addressed for nano-scaled devices.…”

Section: Introductionmentioning

confidence: 99%

Impact of Deep Cryogenic Temperatures on High-k Stacked Dual Gate Junctionless MOSFET Performance: Analog and RF analysis

Ghosh,

Nelapati

2023

Silicon

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This article presents the reliability analysis of a High-k stacked Dual Gate Junction-less MOSFET at Deep Cryogenic Temperatures (as low as 50 Kelvin) in terms of dc, analog and RF stability performance metrics. Furthermore, the dc and analog figure of merits in the presence polarized interface trap charge densities has been analyzed at subambient temperatures. The steep ON-OFF switching and the sub-threshold slope profile shows heavy reliance on temperature variations and confirm that the transistor electrostatics improve at lower temperatures. The study reveals the compatibility of the device to perform at cryogenic temperatures and can be integrated with CMOS technology for quantum computations.

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“…These transistors are known for their doping concentration, constant in the three regions; source, channel and drain, which allow junctionless technology with many advantages, for example, no abrupt junctions, difficult to control at the nanoscale, simpler manufacturing process and volume conduction. This is the probable cause of minimizing of the surface roughness scattering and flicker noise [12][13][14][15].…”

Section: Introductionmentioning

confidence: 99%

Channel Length Effect on Subthreshold Characteristics of Junctionless Trial Material Cylindrical Surrounding-Gate MOSFETs with High-k Gate Dielectrics

Lagraf¹,

Djamil²,

Guergouri³

et al. 2019

J. Nano- Electron. Phys.

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The intensive decrease of channel length for a MOS transistor imposes extensive constraints notably for controlling the short channel effects (SCEs) in nanoscale MOSFET. These constraints can degrade the device performance, hence determining the limits of miniaturization of MOSFET in nanoelectronics applications. In order to reduce the degree of SCEs, a number of new architectures have been reported. Due to their higher scaling capabilities, the double-gate (DG) MOSFETs are expected to be maintained in future nanoelectronics applications. However, with the continuous miniaturization other serious challenges related to the maximum power dissipation and the fabrication cost still persist owing to the high cost techniques used for the elaboration of the p-n junctions. Recently, a new design called junctionless MOSFET without source/drain junctions has been proposed to be an excellent alternative to the conventional MOSFET. The major advantage of this structure resides on the enhanced fabrication procedure through the elimination of the p-n junctions. In this work, the impact of channel length and high-k gate dielectrics materials on the subthreshold characteristics of junctionless trial material cylindrical surrounding-gate MOSFETs (JLTMCSG-MOSFETs) with high-k gate dielectrics and trial material (TM) structure has been studied using two-dimensional analytical model. This model is based on the solution of Poisson's equation in continuous cylindrical regions using superposition method, where the Fourier-Bessel series and separation method have been used to obtain the accurate solution. The performance of low power JLTMCSG-MOSFETs is investigated in terms of surface potential distribution, electrical field, subthreshold current, drain induced barrier lowering (DIBL), subthreshold slope (SS) and threshold voltage (Vth). This study is carried out over a wide range of channel lengths and using high-k gate dielectrics. This study confirms that the analytical model used is useful not only for circuit simulations, but also for device design and optimization for both logic and analog RF circuits applications.

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Analytical subthreshold modeling of dual material gate engineered nano-scale junctionless surrounding gate MOSFET considering ECPE

Cited by 28 publications

References 18 publications

2D analytical modelling of asymmetric junctionless dual material double gate MOSFET for biosensing applications considering steric hindrance issue

2D analytical modelling of asymmetric junctionless dual material double gate MOSFET for biosensing applications considering steric hindrance issue

Impact of Deep Cryogenic Temperatures on High-k Stacked Dual Gate Junctionless MOSFET Performance: Analog and RF analysis

Channel Length Effect on Subthreshold Characteristics of Junctionless Trial Material Cylindrical Surrounding-Gate MOSFETs with High-k Gate Dielectrics

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