Impacts of core gate thickness and Ge content variation on the performance of Si1−xGex source/drain Si–nanotube JLFET

Parameteric optimization of SiGe S/D NT JLFET using analytical modeling to improve L‐BTBT induced GIDL

“…As we introduced the SiGe in source and drain side of NT JLFET which leads to change in the flat band voltage V fb with variation in the Ge content, x and which is given by 24 $$$$ {V}_{\mathrm{f}\mathrm{b}}={\phi}_{\mathrm{m}}-\left(\begin{array}{l}{\phi}_{\mathrm{si}}+{\left(\Delta {E}_{\mathrm{c}}\right)}_{s-\mathrm{si}}{\phi}_{\mathrm{m}}/q\\ {}-{\left(\Delta {E}_{\mathrm{g}}\right)}_{s-\mathrm{si}}/q+{U}_{\mathrm{T}}\ln \left({N}_{\mathrm{V},\mathrm{si}}/{N}_{\mathrm{V},\mathrm{si}-\mathrm{NT}}\right)\end{array}\right)\kern0.5em -\frac{qN_{\mathrm{f}}}{C_{\mathrm{ox}1}} $$$$ …”

“…The high electric field in the lateral direction in nanotube causes tunneling of electrons from valence band of channel region to conduction band of drain region in the OFF‐state which results in the L‐BTBT induced GIDL current. Therefore, GIDL current I GIDL has strong dependance on the electric field and energy band gap as given 24,25 $$$$ {I}_{\mathrm{GIDL}}=\frac{A}{B}\left[{E}_1^2\left({r}_1,{L}_g\right){e}^{\left(-\frac{B}{E_1\left({r}_1,{L}_g\right)}\right)}+{E}_2^2\left({r}_2,{L}_g\right){e}^{\left(-\frac{B}{E_2\left({r}_2,{L}_g\right)}\right)}\right] $$$$ …”

“…In this paper, a novel SiGe source/drain Si‐NT JLFET has been analyzed with geometrical parameters to diminish the effect of GIDL in the sub‐20 nm gate length regimes 8,9 . The insertion of SiGe at the source side and drain side of NT caused the valence band discontinuity which is mainly due to the lattice mismatch results in increased the potential barrier height and tunneling width at the channel‐drain interface and thus limits the tunneling of electrons.…”

Performance enhancement of nanotube junctionless FETs with low doping concentration rings

“…In addition, the researchers propose to utilize the valence band discontinuity of heterojunctions to increase the tunneling width of the NT JLFET. The presence of the heterojunction increases the channel-drain barrier height and tunneling width, thus reducing the I OFF [15][16][17]. The lattice mismatch between SiGe and Si produced the biaxial tensile strain in the channel radially and compressive strain along the channel direction which results in electron mobility degradation above germanium content 30% [16].…”

“…The lattice mismatch between SiGe and Si produced the biaxial tensile strain in the channel radially and compressive strain along the channel direction which results in electron mobility degradation above germanium content 30% [16]. When the channel length of the NT JLFET is less than 10 nm, the presence of the heterojunction interface causes the threshold voltage to decrease dramatically [17]. Researchers used intrinsic pockets to increase the tunneling width of the NT JLFET and decrease the I OFF .…”