Impacts of plasma-induced damage due to UV light irradiation during etching on Ge fin fabrication and device performance of Ge fin field-effect transistors

Abstract

We investigated the impacts of plasma-induced damage due to UV light irradiation during etching on Ge fin fabrication and the device performance of Ge fin field-effect transistors (Ge FinFETs). UV light irradiation during etching affected the shape of the Ge fin and the surface roughness of the Ge fin sidewall. A vertical and smooth Ge fin could be fabricated by neutral beam etching without UV light irradiation. The performances of Ge FinFETs fabricated by neutral beam etching were markedly improved as compared to those of Ge FinFETs fabricated by inductively coupled plasma etching, in which the UV light has an impact.

Sb-doped crystallization of densified precursor for n-type polycrystalline Ge on an insulator with high carrier mobility

“…[1][2][3][4] For both p and n channels, effective mobilities in Ge MOS field-effect transistors (MOSFETs) have exceeded those in Si-MOSFETs because of the development of device technologies including gate stacks. [4][5][6][7][8] The most promising usage of such high-performance Ge-CMOS is to integrate it into Si large-scale integrated circuits (LSIs) or flat-panel displays. To achieve this, low-temperature Ge-on-insulator (GOI) technology has been developed, including solid-phase crystallization (SPC), [9][10][11][12][13] laser annealing, [14][15][16][17][18] chemical vapor deposition, 19,20 flash-lamp annealing, 21 the seed layer technique, 22 and metal-induced crystallization.…”

Advanced solid-phase crystallization for high-hole mobility (450 cm2V−1s−1) Ge thin film on insulator

“…Effective mobilities in Ge metal-oxide-semiconductor field-effect-transistors (MOSFETs) have exceeded those in Si-MOSFETs thanks to the development of device technologies including gate stacks. [1][2][3][4][5][6] Ge on insulator (GOI) technology has been widely studied for lowering the fabrication cost and improving the device performance of Ge-MOSFETs. Researchers have developed many techniques for GOIs, such as mechanical transfer, 7) oxidation-induced condensation, [8][9][10] epitaxial growth on Si on insulator, 11,12) and rapid-melting growth.…”

Management of Phonon Transport in Lateral Direction for Gap-Controlled Si Nanopillar/SiGe Interlayer Composite Materials

“…In general, semiconductor devices need to have low heat generation and low power consumption. To improve the performance of the semiconductor device, a metal-oxide-semiconductor fieldeffect transistor (MOSFET) was designed with miniaturization, changing the structure from planer to Fin and nanosheet, and considering the material such as germanium [7][8][9]. In MOSFET, there are three causes of electron mobility reduction: Coulomb, roughness, and phonons.…”