Impacts of SiN deposition parameters on n-channel metal-oxide-semiconductor field-effect-transistors

Lu, Ching Sen; Lin, Horng–Chih; Huang, Tiao‐Yuan

doi:10.1016/j.sse.2008.06.023

Cited by 1 publication

(1 citation statement)

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“…Among all the feasible strain approaches, SiN capping technique receives much attention because it is easy to execute in modern ultra-large scale integration technology. 17 In addition, strain level ranging from highly tensile to highly compressive is adjustable. In this work, the performance, short channel effects, and simulation results of the devices combining CESL stressor and SiGe channel have been carefully investigated.…”

Section: Introductionmentioning

confidence: 99%

Comparison of NMOSFET and PMOSFET Devices That Combine CESL Stressor and SiGe Channel

Hsu¹,

Huang²,

Lee³

et al. 2013

j. nanosci. nanotech.

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Strained-Si technology could enhance the carrier mobility and improve the device performance. Contact-etch-stop-layer (CESL) structure with different stress and SiGe channel was fabricated with 90-nm technology. The electrical properties of N and PMOSFET devices combining CESL and SiGe channel were investigated. The short channel effects (SCE), such as drain-induced barrier lowering (DIBL), were also studied. Moreover, the stress contour in the SiGe channel has been simulated with TCAD to understand the relationship between stress distribution and device performance for different CESL structures. It is observed that the stress in the channel region was independent of the type of N or PMOSFET devices, but it was dependent on the CESL type and channel length. Based on the experimental and simulation results, it is confirmed that the device performance is associated with the stress in the channel, and the approach of CESL stressor and SiGe channel is shown to effectively improve the mobility of NMOSFETs and PMOSFETs.

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Section: Introductionmentioning

confidence: 99%