“…Thus, it can be stated that, ideally, the cascade connection of n ideal TPVD circuits with Vin[n] = Vout[n- 1] leads to a situation where Vout[n] = 2nVin [1]. Hence, theoretically, a 2-stage (n = 2) cascade connection of TPVD circuits using a 3.3 V battery as input voltage Vin [1] would provide an output voltage Vout [2] = 13.2 V. Actually, the real output voltage V out that can be obtained through the single-stage TPVD architecture depends on many design/application parameters and usually is lower than the result given by the ideal analysis. The size (W k /L k ) of the S k transistors, which is directly related to their on-resistance R dsk values and their parasitic capacitances, the values of C f and C L capacitors, the switching frequency f s = 1/T of CLK k clock signals, the input voltage V in , and the value of the active load R L (which sets the load current I L ) are parameters that have a direct influence in the unregulated steady-state V out value that is really obtained.…”