Implementation of a cycle-based simulator for the design of a processor core

Rim, Moon Gyung; Moon, Byung In; An, Sang Jun; Ryu, Dong Ryul; Lee, Yong Surk

doi:10.1109/apasic.1999.824040

Cited by 3 publications

(1 citation statement)

References 2 publications

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“…Figure 3 In the hardware we are modeling in parallel; various latches operate simultaneously. To properly model the processor using procedural language, we can implement pipelining by executing 6 pipeline in reverse order of data flow [3]. The 6 pipeline functions that indicate 6 pipeline stages include functional blocks implemented by CLASS variable type depending on pipeline operation.…”

Section: Implementation Of Cycle Accurate Modelmentioning

confidence: 99%

A cycle accurate model for a DSP

Park

Kim

Ryu

et al. 2006

2006 International Forum on Strategic Technology

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In this paper, we introduce a implementation method and procedural of the CBS(Cycle Base Simulator), cycle accurate simulation model, which describes the operation of a 24 bit DSP(Digital Signal Processor) at a pipeline cycle level. This tool is some functional abstraction and cycle accurate timing model of target DSP. The CBS can show the data about the internal registers, status flags, data bus, address bus, input and output pin of the DSP, and also the control signals at each pipeline cycle. The design procedure has been carried out by the following procedure, analysis of target DSP specification, implementation of function block, design of pipeline, design of instruction decoder, and implementation of the instructions. We model the DSP with high level language C++ before the hardware design gets started with HDL to investigate the performance of the DSP. We verified the CBS by running all instructions of DSP and two application programs. The CBS will be used as a reference of logic simulation of the DSP and in RTL model verification under Co-Simulation environment.

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Section: Implementation Of Cycle Accurate Modelmentioning

confidence: 99%

A cycle accurate model for a DSP

Park

Kim

Ryu

et al. 2006

2006 International Forum on Strategic Technology

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Efficient random vector verification method for an embedded 32-bit RISC core

Lee

Yang²,

Kwak³

et al.

Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)

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Processors require both intensive and extensive functional verification in their design phase to satisb their general purposability. The proposed random vector verification method for CalmRISCTM-32 core meets this goal by contributing complementary assistance for conventional verification methods. It adopts a cycle-accurate instruction level simulator as a reference model, runs simulation in both the reference and the target HDL and reports errors ifany difference is found between them. These processes are automatically performed in the unifed environment. The instruction level simulator, the core part in the verijkation environment is able to simulate almost every aspect of RISC processors from functional behavior of each opcode to timing details in the pipeline flow in fast speed. Its design style from microprogramming scheme also makes its structure modular and flexible.

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A compact DSP architecture for digital audio

Ryu

Park

et al. 2008

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems

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Implementation of a cycle-based simulator for the design of a processor core

Cited by 3 publications

References 2 publications

A cycle accurate model for a DSP

A cycle accurate model for a DSP

Efficient random vector verification method for an embedded 32-bit RISC core

A compact DSP architecture for digital audio

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