Implementation of a double-precision multiplier accumulator with exception treatment to a dense matrix multiplier module in FPGA

Abstract

Recently, the manufactures of supercomputers have made use of FPGAs to accelerate scientific applications [16] [17]. Traditionally, the FPGAs were used only on non-scientific applications. The main reasons for this fact are: the floating-point computation complexity; the FPGA logic cells are not sufficient for the scientific cores implementation; the cores complexity prevents them to operate on high frequencies.Nowadays, the increase of specialized blocks availability in complex operations, as sum and multiplier blocks, implemented directly in FPGA and, the increase of internal RAM blocks (BRAMs) have made possible high performance systems that use FPGA as a processing element for scientific computation [2].These devices are used as co-processors that execute intensive computation. The emphasis of these architectures is the exploration of parallelism present on scientific computation operations and data reuse.In major of these applications, the scientific computation uses, in general, operations of big floating-point dense matrices, which are normally operated by MACs.In this work, we describe the architecture of an accumulative multiplier (MAC) in double precision floating-point, according to IEEE-754 standard and we propose the architecture of a multiplier of matrices that uses developed instances of the MACs and explores the reuse of data through the use of the BRAMs (Blocks of RAM internal to the FPGAs) of a Xilinx Virtex 4 LX200 FPGA. The synthesis results showed that the implemented MAC could reach a performance of 4GFLOPs.

An FPGA-Based Accelerator to Speed-Up Matrix Multiplication of Floating Point Operations

“…The MAC has a pipeline with 33 stages. Since the data reuse strategy proposed in [4] substantially reduced the data access bottleneck, the number of MACs that can be instantiated in the FPGA is limited by the number of DSP blocks in the FPGA [5].…”

Architecture for dense matrix multiplication on a high-performance reconfigurable system

“…Hence, the order of matrices operated have to meet the condition The second consideration is the compromise between the number of MACs (which is limited by the amount of DSPs blocks in the FPGA) [17] and the memory bandwidth available in the architecture, given by…”

“…• the processing block is similar to the one presented in Figure 4 and uses accumulative multipliers (MACs) in double precision floating-point, according to IEEE-754 standard [17]. The Figure 6 shows a block diagram of the developed architecture.…”

Uma abordagem de alto desempenho para multiplicação de matrizes densas em sistemas reconfiguráveis

“…• O bloco de processamento é similar ao apresentado na Figura 5 e utiliza multiplicadores acumuladores (MACs) de ponto-flutuante precisão dupla, de acordo com o padrão IEEE-754 [18].…”

“…é o número de palavras que podem ser armazenadas nas BRAMs; A segunda consideração é o compromisso que deve existir entre o número de MACs (que é limitada pela quantidade de blocos de DSP)[18] e a largura de banda disponível na arquiteturaonde bw é a largura de banda da memória em bits por segundo, k é o número de MACs, , f é a freqüênciade operação do FPGA e DSP MAC N _ é o número máximo de MACs que podem ser instanciados no FPGA usando os DSPs disponíveis.…”