Implementation of a Fourth-Generation 1.8-GHz Dual-Core SPARC V9 Microprocessor

Hart, J.; Lee, K.T.; Chen, D.; Cheng, Lik; Chou, Chipai; Dixit, Ashutosh; Greenley, D.; Gruber, G.; Ho, Kuan-Hsien; Hsu, J.; Malur, N.G.; Wu, Chih-Hang John

doi:10.1109/jssc.2005.859895

Cited by 20 publications

(5 citation statements)

References 5 publications

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“…Based on the above classification, as the sum of "control circuitry" and "operational circuitry" normally determines the "total cost" of a processor design, an inevitable trade-off between performance, cost, and flexibility arises. Figure 1 shows the Control versus Operational circuitry Ratio (COR) observation of several representative processor implementations estimated from their die photos [1,6,10,12], demonstrating a fairly accurate match between the COR value of each processor category and its well-known flexibility degree: the larger the COR, the higher the degree of flexibility. As the same trade off between performance and flexibility will inevitably occur also for any design choices taken by in-vehicle vision processors, the design of an in-vehicle vision processor is usually an optimizing search process of a compromised combination of performance and flexibility fulfillment under the severe in-vehicle cost constraints, such as consuming less than 2 W of power while hopefully achieves several hundreds of GOPS performance against as many vision applications as possible.…”

Section: Introductionmentioning

confidence: 89%

IMAPCAR: A 100 GOPS In-Vehicle Vision Processor Based on 128 Ring Connected Four-Way VLIW Processing Elements

Kyo

Okazaki

2008

J Sign Process Syst

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This paper presents IMAPCAR, a 100GOPS programmable highly parallel vision processor LSI consuming less than 2 W of power for in-vehicle vision tasks of driver assistance systems. First, requirements of vision processors for driver assistance systems as well as the characteristics of vision tasks for safety are summarized. Next, features in the design of IMAPCAR are described in detail, which comparing with a previous design, improved the performance for major vision tasks by a factor of 2.5 while reduced 50% of power. Design choices taken by other in-vehicle vision processors are also compared and analyzed. Finally, technology perspectives of future invehicle vision processors are discussed.

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Section: Introductionmentioning

confidence: 89%

IMAPCAR: A 100 GOPS In-Vehicle Vision Processor Based on 128 Ring Connected Four-Way VLIW Processing Elements

Kyo

Okazaki

2008

J Sign Process Syst

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“…Very high-performance microprocessors [Xanthopoulos et al 2001;Restle et al 2002;Thomson et al 2006;Hart et al 2006] address this by overdesigning uniform meshes so that small changes in load capacitance do not significantly affect the mesh skew. This, however, significantly increases the power of the entire clock network and is unwanted for high-performance, low-power ASIC designs which are the focus of this work.…”

Section: Nonuniform Advantages and Disadvantagesmentioning

confidence: 99%

“…Clock structures with redundancy such as meshes (also known as grids) [Venkataraman et al 2006;Rajaram and Pan 2010;Desai et al 1996;Hu and Guthaus 2011], spines, and cross-links [Venkataraman et al 2005] are an effective way to reduce skew variation. For this reason, many microprocessor designs such as a 1.2 GHz Alpha processor [Xanthopoulos et al 2001], the Power4 [Restle et al 2002], the Power6 [Thomson et al 2006], and a dual-core SPARC V9 [Hart et al 2006] use clock meshes. Mesh-based clock distribution architectures are also supported by commercial tools in ASIC design flows [Cadence 2005].…”

Section: Introductionmentioning

confidence: 99%

High-performance clock mesh optimization

Guthaus

Wilke

et al. 2012

ACM Trans. Des. Autom. Electron. Syst.

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Clock meshes are extremely effective at producing low-skew regional clock networks that are tolerant of environmental and process variations. For this reason, clock meshes are used in most high-performance designs, but this robustness consumes significant power. In this work, we present two techniques to optimize high-performance clock meshes. The first technique is a mesh perturbation methodology for nonuniform mesh routing. The second technique is a skew-aware buffer placement through iterative buffer deletion. We demonstrate how these optimizations can achieve significant power reductions and a near elimination of short-circuit power. In addition, the total wire length is decreased, the number of required buffers is decreased, and both skew and robustness are improved on average when variation is considered.

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“…Many microprocessor designs use clock meshes to reduce the clock skew due to variations and design mismatch, e.g., the first generation Itanium [5], 1.2GHz Alpha processor [6], Power4 [7], Dual-Core SPARC V9 [8] and the Power6 microprocessor [9]. Mesh-based clock distribution architectures are also supported by commercial tools in the ASIC design flow [1].…”

Section: Introductionmentioning

confidence: 99%

A Mesh-Buffer Displacement Optimization Strategy

Flach

Wilke

Johann

et al. 2010

2010 IEEE Computer Society Annual Symposium on VLSI

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Clock meshes are an important resource for high performance circuit designers due to its robustness to variability. Until recently, there were no tools able to support the use of clock meshes in automated synthesis flows. In the last years commercial tools were adapted to support clock meshes [1] and the academia has addressed the problems of clock mesh design automation and optimization. However, current optimization techniques are still very preliminary. Many other aspects of the clock mesh design can be explored besides of edge removal and buffer placement explored by [2] and [3]. This paper proposes an algorithm to move the mesh buffers over the mesh wires to a position that minimizes the clock skew at the clock sinks. Experimental data show significant skew reduction using the algorithm presented in this paper. The clock mesh area and capacitance are unaffected by this strategy, therefore no overhead is introduced.

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Implementation of a Fourth-Generation 1.8-GHz Dual-Core SPARC V9 Microprocessor

Cited by 20 publications

References 5 publications

IMAPCAR: A 100 GOPS In-Vehicle Vision Processor Based on 128 Ring Connected Four-Way VLIW Processing Elements

IMAPCAR: A 100 GOPS In-Vehicle Vision Processor Based on 128 Ring Connected Four-Way VLIW Processing Elements

High-performance clock mesh optimization

A Mesh-Buffer Displacement Optimization Strategy

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