Implementation of a reconfigurable neural network in FPGA

Oliveira, Janaina G. M.; Moreno, Robson Luiz; Dutra, Odilon O.; Pimenta, Tales Cleber

doi:10.1109/iccdcs.2017.7959699

Cited by 10 publications

(4 citation statements)

References 6 publications

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“…Of course, additional latency, in this case as well, is introduced by the interconnect hierarchy. Nevertheless, the presented approach performs better than [27]. The results in Table 2 suggest that the developed approach excels at maximizing NN throughput.…”

Section: Comparison With Other Approachesmentioning

confidence: 90%

“…A reconfigurable neural network architecture, composed of 20 neurons, is proposed in [27]. Architecture is divided into four parts: instructions unit, memory unit, layer unit and controller unit.…”

Section: Related Workmentioning

confidence: 99%

“…FFNN resource use, implementation details and comparison with related work [23,24,26,27] are illustrated in Table 2. "Target Initiation Interval" denotes the targeted number of cycles for each pipeline stage which is fed into FFNN generation tool for throughput optimization.…”

Section: Comparison With Other Approachesmentioning

confidence: 99%

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An Approach of Feed-Forward Neural Network Throughput-Optimized Implementation in FPGA

et al. 2020

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Artificial Neural Networks (ANNs) have become an accepted approach for a wide range of challenges. Meanwhile, the advancement of chip manufacturing processes is approaching saturation which calls for new computing solutions. This work presents a novel approach of an FPGA-based accelerator development for fully connected feed-forward neural networks (FFNNs). A specialized tool was developed to facilitate different implementations, which splits FFNN into elementary layers, allocates computational resources and generates high-level C++ description for high-level synthesis (HLS) tools. Various topologies are implemented and benchmarked, and a comparison with related work is provided. The proposed methodology is applied for the implementation of high-throughput virtual sensor.

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Section: Comparison With Other Approachesmentioning

confidence: 90%

Section: Related Workmentioning

confidence: 99%

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An Approach of Feed-Forward Neural Network Throughput-Optimized Implementation in FPGA

et al. 2020

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“…Oliveira et al [53] implemented a 4×8×3×3 MLP Iris problem using 90 clock cycles and 77.8MHz, whereas our architecture would do it using 51 cycles at 490MHz at lower memory usage.…”

Section: Discussionmentioning

confidence: 99%

A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration of Feedforward Neural Networks

et al. 2019

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New chips for machine learning applications appear, they are tuned for a specific topology, being efficient by using highly parallel designs at the cost of high power or large complex devices. However, the computational demands of deep neural networks require flexible and efficient hardware architectures able to fit different applications, neural network types, number of inputs, outputs, layers, and units in each layer, making the migration from software to hardware easy. This paper describes novel hardware implementing any feedforward neural network (FFNN): multilayer perceptron, autoencoder, and logistic regression. The architecture admits an arbitrary input and output number, units in layers, and a number of layers. The hardware combines matrix algebra concepts with serial-parallel computation. It is based on a systolic ring of neural processing elements (NPE), only requiring as many NPEs as neuron units in the largest layer, no matter the number of layers. The use of resources grows linearly with the number of NPEs. This versatile architecture serves as an accelerator in real-time applications and its size does not affect the system clock frequency. Unlike most approaches, a single activation function block (AFB) for the whole FFNN is required. Performance, resource usage, and accuracy for several network topologies and activation functions are evaluated. The architecture reaches 550 MHz clock speed in a Virtex7 FPGA. The proposed implementation uses 18-bit fixed point achieving similar classification performance to a floating point approach. A reduced weight bit size does not affect the accuracy, allowing more weights in the same memory. Different FFNN for Iris and MNIST datasets were evaluated and, for a real-time application of abnormal cardiac detection, a ×256 acceleration was achieved. The proposed architecture can perform up to 1980 Giga operations per second (GOPS), implementing the multilayer FFNN of up to 3600 neurons per layer in a single chip. The architecture can be extended to bigger capacity devices or multi-chip by the simple NPE ring extension.INDEX TERMS Feedforward neural networks -FFNN, systolic hardware architecture, FPGA implementation, neural network acceleration, deep neural networks.

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A Hardware Accelerator Implementation of Multilayer Perceptron

Thasnimol

George

2021

Advances in Intelligent Systems and Computing

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Implementation of a reconfigurable neural network in FPGA

Cited by 10 publications

References 6 publications

An Approach of Feed-Forward Neural Network Throughput-Optimized Implementation in FPGA

An Approach of Feed-Forward Neural Network Throughput-Optimized Implementation in FPGA

A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration of Feedforward Neural Networks

A Hardware Accelerator Implementation of Multilayer Perceptron

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