Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability

Hwang, Wei; Gristede, George; Sanda, P. N.; Wang, S.Y.; Heidel, D.

doi:10.1109/4.777109

Cited by 32 publications

(12 citation statements)

References 19 publications

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“…Though many efforts have been focused on the improvement of adder and multiplier designs, [8,9,11], to challenge the GHz operations, the major trade-off of these GHz logic circuits is the high power consumption which is not a tolerable price to pay in recent mobile technologies [3,10]. Besides adders, digital multipliers are the most critical arithmetic functional unit in many DSP applications, e.g., Fourier Transform, DCT, filtering, etc.…”

mentioning

confidence: 99%

Low-Power Multiplier Design Using a Bypassing Technique

Wang

2008

J Sign Process Syst Sign Image Video Technol

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This paper presents a low power digital multiplier design by taking advantage of a 2-dimensional bypassing method. The proposed bypassing cells constituting the multiplier skip redundant signal transitions as well as computations when the horizontally partial product or the vertical operand is zero. Hence, it is a 2-dimensional bypassing method. Thorough post-layout simulations of a 8×8 digital multiplier using the proposed 2-dimensional bypassing method show that the power dissipation of the proposed design is reduced by more than 75% compared to prior designs. Physical measurements on silicon reveal that the proposed digital multiplier saves more than 28% even with pads' power dissipation compared to the prior works.

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mentioning

confidence: 99%

Low-Power Multiplier Design Using a Bypassing Technique

Wang

2008

J Sign Process Syst Sign Image Video Technol

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“…Various forms of Self-Reset logic have been proposed in recent years. In globally self-resetting CMOS [4], the reset signal for each stage is generated by a separate timing chain which provides a parallel worst-case delay path. On the other hand, in locally self-resetting CMOS [5], the reset signal for each stage is generated by a mechanism internal to that stage.…”

Section: Design Overviewmentioning

confidence: 99%

A Novel Pseudo 4 Phase Dual Rail Asynchronous Protocol With Self Reset Logic & Multiple Reset

Narayanan¹,

Kumar²,

Kalish³

et al. 2010

IJCA

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This paper presents a novel pseudo 4-phase dual-rail protocol with self-reset logic suited for high speed asynchronous applications. The traditional 4-phase dual-rail requires the input to be of alternating valid and empty cycles. However the proposed pseudo 4-phase involves continuous stream of valid data without a separate empty cycle. The empty phase is generated internally so that the next valid data can be processed. Also self-reset logic for dual-rail protocol has been proposed in which the combinational blocks resets itself whenever its evaluation phase is completed and the data is latched at the pipeline register. The concept of multiple-reset i.e. resetting each of the gates in the combinational block between any two pipeline registers simultaneously has been introduced reducing the reset phase and hence increasing the throughput rate. An asynchronous 8-bit pipelined carry propagate adder was implemented in 0.18μm technology. The reset phase has reduced by 63.25% and 47.63% compared to the design without self and multiple reset for logic depth of three and two respectively. The results show that the reset phase varies inversely with the logic depth for the proposed design.

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“…Since our logic is implemented using standard CMOS cell libraries, it is free of any device sizing issues that are often needed to insure correct operation. In addition, no stringent timing requirements are imposed on inputs and outputs as opposed to the approaches in [2,3].…”

Section: Introductionmentioning

confidence: 99%

Self-resetting stage logic pipelines

Ejnioui

Alsharqawi

2004

Proceedings of the 14th ACM Great Lakes Symposium on VLSI

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In this paper, we present a novel synchronization approach to support data flow in clockless designs using single-rail encoding. This approach is based on self-resetting stage logic in which a pipeline stage resets itself before starting the next execution cycle. As such, a stage goes through a reset phase when its output is null, and an evaluate phase when its output is the result of the evaluation of its inputs. To insure correct operation, a pipeline stage is ready to absorb inputs from a previous stage if it is in the reset phase. As a result, data flow from one stage to another when the preceding stage is in the evaluate phase while the following stage is in the reset phase. To support this data flow, a latch-based synchronization mechanism is proposed. This mechanism yields an efficient and simple uni-directional handshaking scheme between stages that allows for easy implementation. This handshaking scheme is extended to handle the join and forks of data flows encountered in non-linear pipelines. A concept design of a four-bit 16-stage pipeline is presented to illustrate the inner workings of self-resetting stage logic and its data-flow synchronization mechanism. The pipeline performance is examined through a detailed signal timing analysis. This analysis reveals some insights on how the duration of the evaluate phase gradually increases while the duration of the reset phase and the latch enable gradually decreases toward the left stages of the pipeline. This gradual decrease in the duration of the enable of the latches between stages is used to derive a bound on the maximum possible depth of the pipeline.

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Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability

Cited by 32 publications

References 19 publications

Low-Power Multiplier Design Using a Bypassing Technique

Low-Power Multiplier Design Using a Bypassing Technique

A Novel Pseudo 4 Phase Dual Rail Asynchronous Protocol With Self Reset Logic & Multiple Reset

Self-resetting stage logic pipelines

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