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This paper presents a fast, low-power, binary carrylookahead, 64-bit dynamic parallel adder architecture for highfrequency microprocessors. The adder core is composed of evaluate circuits and feedback reset chains implemented by selfresetting CMOS (SRCMOS) circuits with enhanced testability. A new tool, SRCMOS pulse analyzer (SPA), is developed for checking dynamic circuits for proper operation and performance. The nominal propagation delay and power dissipation of the adder were measured to be 1.5 ns (at 22 C with V V V dd = = = 2:5 V) and 300 mW. The adder core size is 1.6 2 2 2 0.275 mm 2. The process technology used was the 0.5-m IBM CMOS5X technology with 0.25-m effective channel length and five layers of metal. The circuit techniques are easily migratable to multigigahertz microprocessor designs. Index Terms-Adder, CMOS, CMOS digital integrated circuits, dynamic logic circuits, high-speed integrated circuits, integrated circuit design, microprocessors, self-resetting CMOS (SRCMOS).