Implementation of CMP-based design rules and patterning practices

Abstract

This paper discusses specific die patterning techniques utilized during the implementation of a CMP-based BEOL within Digital's Alpha technologies. Customary application of inter-level dielectric (ILD) CMP, to eliminate topographically induced defect mechanisms and increase photolithographic focal budget margins, came with it for Alpha, the need to strictly control both inter-and intra-die dielectric capacitance and thickness. To this end, several die patterning strategies were used to minimize the feature size and pattern density dependencies of ILD CMP as well as aid in the fast paced evolution from test vehicle to product chip reticles. Quantification of inter-level and intra-die thickness control with respect to ghost/partial die patterning, zero level (ZL) and perimeter bordering, dummy/filler feature patterning and general CMP-based design rules will he addressed within the context of analysis of variance (ANOVA). Further discussed will be the empirical rules-of-thumb and critical dimension (CD) variance definitions which provided the planarity targets utilized throughout the framework of these experiments.

IC layout and manufacturability: critical links and design flow implications

“…Since bounding the density in windows of a dissection can 1 In oxide polishing of interlayer dielectrics, the pad conforms to local topography and overpolishes empty o xide areas that have n o underlying metal features dishing"; areas with dense underlying metal features are underpolished. The typical oxide thickness variation of up to 4000 angstroms uses up a large fraction of the die's variability budget 14 44 45 .…”

“…In very deep-submicron VLSI, manufacturing steps involving chemical-mechanical polishing CMP have varying e ects on device and interconnect features, depending on local characteristics of the layout. 1 Recent work in statistical metrology shows that CMP variation is controlled if the local feature density is controlled 37 46 . 2 Post-CMP oxide thickness is monotone in feature density, s o v ariation of local feature density m ust be minimized.…”

Filling algorithms and analyses for layout density control

“…However, such simultaneous constraints may be required in the future e.g., for reverse-active area masks , and we analyze ll pattern synthesis for such a situation in Section 4. 5 The value of slack W will depend on the maximum possible ll pattern density. That is, total empty area outside the bu er distance B from any feature should be scaled by the maximum possible ll density to yield the slack of the window.…”

“…slack W slack of a given w w window W, i.e. the maximum amount of ll area that can be introduced into W. 5 An extremal-density window is a window with either maximum density or minimum density o ver all windows in the layout. If an algorithm applies to either maximum-density or minimum-density analysis, we generically refer to extremal-density analysis.…”

Detailed Placement for Enhanced Control of Resist and Etch CDs

“…To achieve this goal, the layout must be made uniform with respect to a certain density parameter. The physics of semiconductor processing make predictable and uniform manufacturing difficult [5], [14], [35], [53]. In particular, the quality of post-CMP depends on the pattern density of the layer beneath a given dielectric layer.…”