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In oxide chemical-mechanical polishing (CMP) processes, layout pattern dependent variation in the interlevel dielectric (ILD) thickness can reduce yield and impact circuit performance. Metal-fill patterning practices have emerged as a technique for substantially reducing layout pattern dependent ILD thickness variation. We present a generalizable methodology for selecting an optimal metal-fill patterning practice with the goal of satisfying a given dielectric thickness variation specification while minimizing the added interconnect capacitance associated with metal-fill patterning. Data from two industrialbased experiments demonstrate the beneficial impact of metalfill on dielectric thickness variation, a 20% improvement in uniformity in one case and a 60% improvement in the other case, and illustrate that pattern density is the key mechanism involved. The pros and cons of two different metal-fill patterning practices-grounded versus floating metal-are explored. Criteria for minimizing the effect of floating or grounded metal-fill patterns on delay or crosstalk parameters are also developed based on canonical metal-fill structures. Finally, this methodology is illustrated using a case study which demonstrates an 82% reduction in ILD thickness variation. Index Terms-Chemical-mechanical polishing (CMP), design for manufacturing, metal-fill, within-die variation. I. INTRODUCTION I N recent years, chemical-mechanical polishing (CMP) has emerged as the primary technique for planarizing interlayer dielectrics [1], [2]. Although CMP is very effective at reducing the as-deposited step height and achieves a measure of global planarization not possible with either spin-on or resist etchback Manuscript

This paper discusses specific die patterning techniques utilized during the implementation of a CMP-based BEOL within Digital's Alpha technologies. Customary application of inter-level dielectric (ILD) CMP, to eliminate topographically induced defect mechanisms and increase photolithographic focal budget margins, came with it for Alpha, the need to strictly control both inter-and intra-die dielectric capacitance and thickness. To this end, several die patterning strategies were used to minimize the feature size and pattern density dependencies of ILD CMP as well as aid in the fast paced evolution from test vehicle to product chip reticles. Quantification of inter-level and intra-die thickness control with respect to ghost/partial die patterning, zero level (ZL) and perimeter bordering, dummy/filler feature patterning and general CMP-based design rules will he addressed within the context of analysis of variance (ANOVA). Further discussed will be the empirical rules-of-thumb and critical dimension (CD) variance definitions which provided the planarity targets utilized throughout the framework of these experiments.

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