“…p1 NL , second non-dominant pole ! p2 NL and GBW NL are given by (8), (9), (10) and (11), respectively. Dominant pole !…”
Section: Digitally Enhanced Low-drop Out Voltage Regulator Designmentioning
confidence: 99%
“…The work presented in [8] makes use of a Miller compensated error amplifier and pole-zero cancellation technique to ensure stability under load modulations. In [9], diode-like PMOS transistor are used as replacement of resistors located at LDO's loop, providing higher resistance values saving silicon area and decreasing the feedback loop current consumption.…”
“…p1 NL , second non-dominant pole ! p2 NL and GBW NL are given by (8), (9), (10) and (11), respectively. Dominant pole !…”
Section: Digitally Enhanced Low-drop Out Voltage Regulator Designmentioning
confidence: 99%
“…The work presented in [8] makes use of a Miller compensated error amplifier and pole-zero cancellation technique to ensure stability under load modulations. In [9], diode-like PMOS transistor are used as replacement of resistors located at LDO's loop, providing higher resistance values saving silicon area and decreasing the feedback loop current consumption.…”
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