“…Optimization of multisine with 11 components i = [1,2,3,4,5,6,7,8,9,10,11] gives CF = 1.372 at optimal phases In the case where all the initial phases are zero, the CF increases to 2.39 (only 3.42 % higher in comparison with optimal phases).…”
Section: ) Examplementioning
confidence: 93%
“…In [8], it was proposed to use external SRAM memory resources to solve the problem of on-chip memory lack. However, outside memory is not always possible to use on a variety of reasons, e.g., lack of PCB area or power budget limitations.…”
“…It is shown that using a single sine wave generation algorithmic approach for producing multisine wave requires multiple instances of such generator. This is not feasible for implementation on FPGA [7], [8]. In order to reduce the memory footprint of signal to be stored, different techniques as compression and reduction of resolution or sampling rate, are available.…”
“…Requirements for hardware and data compression method were analyzed in [7]. A look-up table suitable for FPGA based implementations was proposed in [8]. Feasibility of multisine generation with limited precision is analyzed in the last section of the paper.…”
Multisine excitation is widely used in impedance measurements to retain the advantages of the sine wave, while reducing the measurement time. To keep the crest factor (CF) of the excitation signal low, the initial phases of the signal components must be optimized. This paper focuses in further optimization of multisine signal for improving the signal-to-noise ratio (SNR) of measurements, reducing the complexity of signal generation and minimizing a memory footprint of the FPGA based implementation.
“…Optimization of multisine with 11 components i = [1,2,3,4,5,6,7,8,9,10,11] gives CF = 1.372 at optimal phases In the case where all the initial phases are zero, the CF increases to 2.39 (only 3.42 % higher in comparison with optimal phases).…”
Section: ) Examplementioning
confidence: 93%
“…In [8], it was proposed to use external SRAM memory resources to solve the problem of on-chip memory lack. However, outside memory is not always possible to use on a variety of reasons, e.g., lack of PCB area or power budget limitations.…”
“…It is shown that using a single sine wave generation algorithmic approach for producing multisine wave requires multiple instances of such generator. This is not feasible for implementation on FPGA [7], [8]. In order to reduce the memory footprint of signal to be stored, different techniques as compression and reduction of resolution or sampling rate, are available.…”
“…Requirements for hardware and data compression method were analyzed in [7]. A look-up table suitable for FPGA based implementations was proposed in [8]. Feasibility of multisine generation with limited precision is analyzed in the last section of the paper.…”
Multisine excitation is widely used in impedance measurements to retain the advantages of the sine wave, while reducing the measurement time. To keep the crest factor (CF) of the excitation signal low, the initial phases of the signal components must be optimized. This paper focuses in further optimization of multisine signal for improving the signal-to-noise ratio (SNR) of measurements, reducing the complexity of signal generation and minimizing a memory footprint of the FPGA based implementation.
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