Implementation of partial synchronization of different chaotic systems by field programmable gate array

Abstract

Abstract-In this study, the synchronization of the masterslave systems has been achieved and implemented on Field Programmable Gate Array (FPGA). In this paper, the master system and the slave system have been chosen as Lorenz and Rossler systems, respectively. The feedback control rule has been derived by feedback linearization method. By feedback linearization, the coordinate transformation has been achieved then the control command for synchronization has been obtained. In order to implement designed synchronized system, Matlab Simulink design of the system has been translated to Xilinx System Generator design to generate Very-High-Speed Integrated Circuits Hardware Description Language (VHDL) code which is used to produce bitstream file. By Xilinx Integrated Software Environment (ISE) program, VHDL code is converted to bitstream file which has been embedded into FPGA by Field Upgradeable Systems Environment (FUSE). Finally, the designed synchronized system has been observed on the HP 54540C oscilloscope.

A novel high speed Artificial Neural Network–based chaotic True Random Number Generator on Field Programmable Gate Array

“…In addition, it has a faster design process and better modification amount compared with PLD. Unlike ASIC, it is a reprogrammable device, ie, many FPGAs can be freely reprogrammed by downloading a different configuration into itself, and modifications can be made on the original design . Moreover, since there is no need to draw and produce an integrated circuit (IC) for each design, FPGA has more flexible design than ASIC …”

“…Unlike ASIC, it is a reprogrammable device, ie, many FPGAs can be freely reprogrammed by downloading a different configuration into itself, and modifications can be made on the original design. [43][44][45] Moreover, since there is no need to draw and produce an integrated circuit (IC) for each design, FPGA has more flexible design than ASIC. [43][44][45] Since FPGA is a device that has a feature of inherent parallelism, it is quite convenient to use this device for the hardware applications of ANN.…”

“…[43][44][45] Moreover, since there is no need to draw and produce an integrated circuit (IC) for each design, FPGA has more flexible design than ASIC. [43][44][45] Since FPGA is a device that has a feature of inherent parallelism, it is quite convenient to use this device for the hardware applications of ANN. ANN-based applications on FPGA can be separated into mainly two groups: the applications of offline training and online training.…”