Implementation of Realtime and Highspeed Phase Detector on FPGA

Guntoro, Andre; Zipf, Peter; Soffke, Oliver; Klingbeil, Harald; Kumm, Martin; Glesner, Manfred

doi:10.1007/11802839_1

Cited by 6 publications

(2 citation statements)

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“…Table IV shows the synthesized result comparison of the proposed design with the previous design in fixed-point on the silicon technology. Since the previous design, pipelining fixed-point [6], is 16-bit computation, but the proposed design is 32-bit, the VI. CONCLUSION This paper proposes the floating-point pipelining CORDIC architecture compliance to the IEEE standard single precision in order to detect the phase and magnitude between the RF signal and the beam signal of the closed-loop control system.…”

Section: Floating-point Architecturementioning

confidence: 98%

“…At initial phase of this project, the close-loop control system was operated by sequential programs based on a single processor, DSP, where the phase and magnitude detection task had been included and executed by the DSP [5]. To reduce critical tasks and alleviate high traffic on the DSP, A. Guntoro et al had implemented a high-speed phase detector on FPGA based on fixed-point operations [6]. The pipelining architecture of the phase detector is able to increase the computing performance of the phase detection dramatically with cooperating hardwaresoftware compared to pure software.…”

Section: Introductionmentioning

confidence: 99%

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Pipelined Floating-Point Architecture for a Phase and Magnitude Detector Based on CORDIC

Surapong

Glesner

2011

2011 21st International Conference on Field Programmable Logic and Applications

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To improve the computation precision of the beams control system in a heavy ion accelerator system, a floating-point phase and magnitude digital detector is proposed. The coordinate rotation digital computer (CORDIC) algorithm is utilized to compute results in digital form. Due to the hardware design simplicity, shifting and adding operations become two main operators to perform the computation. The proposed CORDIC core is based on floating-point arithmetic units to obtain high accuracy for the closed-loop control system. A Pipeline-based architecture is applied instead of CORIDC's iteration process in order to maximize computation performance. Moreover, comparison of hardware 8-and 16-stage pipeline-based simulations with Matlab/simulink is statically analysis to differentiate the accuracy of the two hardware architectures. Finally, resource efficiencies based on target Xilinx FPGA xc5vlx110 and 130-nm Silicon technology are shown that 8-and 16-stage hardwares consume maximum 18% and 38% of total slices at 134 MHz on the target FPGA, as well as 43,164 µm 2 and 83,769 µm 2 at 617 MHz on Silicon technology.

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Section: Floating-point Architecturementioning

confidence: 98%

Section: Introductionmentioning

confidence: 99%