Since the development of the electronic transistor 60 years ago its technical utilization has revolutionized modern society. Consequent miniaturization was the key to this development. The challenge to develop flat printable electronics based on inorganic materials could give this area further input. It could be the basis for flexible displays or electronic paper when the active material is processable from solution, shows very good adherence to flexible substrates and excellent physical performance.[1] To meet these challenges any material considered requires a tuned set of functional properties. In general inorganic semiconductors are in advantage over organic materials as far as their physical performance is concerned. However, often processing and adherence to substrates is a problem with inorganic semiconductors. ZnO is available in various morphologies as transparent oxide, is non toxic, inexpensive and has shown promising physical semiconductor properties. [2][3][4] For solution processedZnO field-effect transistor (FET) devices, the highest electron mobility values are currently 1.65 cm 2 V À1 s À1 , however obtainable only after calcinations at temperatures >300 8C.[5] So far, despite promising physical performance parameters, neither synthesis conditions, nor processing techniques are yet compatible with existing printing technologies envisioned for flexible printing of ZnO semiconductors on polymer substrate basis. Currently the utmost challenge in the field is to gain a most complete understanding of the interplay between the parameters synthesis, processing and semiconductor performance for future development of printable electronic devices based on inorganic semiconductors such as ZnO. Despite a couple of recent reports on the deposition of zinc oxide thin layers in FET devices, processing from solution and conversion into the active FET channel electrode under fairly mild conditions is a great challenge. Chemical bath deposition techniques [6,7] and sol-gel processes were mainly investigated in this regard. [5,[8][9][10] However, both techniques typically require either high processing temperatures (above 300 8C) or long reaction times and are thus inappropriate for printing applications on flexible polymer based substrates under state of the art printing conditions. Processing temperatures well below 200 8C are the goal for the formation of semiconducting inorganic thin films onto such substrates. The application of soft processes like spin or dip coating or any kind of printing or stamping rely on the formation and adherence of such thin films on flexible substrates. Herein we report our investigations on the formation, characterization, low temperature processing and printing behavior of a molecular precursor and its conversion to unifom ZnO thin films and promising electronic performance of such films in an FET device.Our process starts from a modified synthesis of the ZnO single source precursor bis [2-(methoxyimino)propanoato]zinc 1 [11,12] (Scheme 1) which we developed for depositing thin tr...

In this paper we introduce a design methodology that allows the system/circuit designer to build reliable systems out of unreliable nano-scale components. The central point of our approach is a generic (parametrical) architectural template, COnfigurable Nanostructures for reliAble Nano electronics (CONAN), which embeds support for reliability at various levels of abstractions. Some of the main reliability sources are regular and decentralized structures based on simple basic computation cells designed to be robust against disturbances and noise, fault tolerance based on hardware, time and information redundancy applied at the basic cell level as well as at higher levels, self diagnosis assisted by the dynamic reconfiguration of basic computation cells and interconnect rerouting. Within the CONAN template both technology dependent and independent models co-exists such that the more abstract layers are technology independent while the lower levels can be retargeted to various fabrication technologies. Our proposal is applicationoriented and allows the designers to deal with unpredictability, and low reliability, which are unavoidable characteristics of future emerging nano-devices. When combined with the underlying software, the tools supporting the CONAN approach allow the designer to check whether the design constraints are fulfilled before performing a detailed implementation and provides means to trade area, delay, and power consumptions for reliability. As such, this proposal is a call-to-arms to mobilize the efforts of systems designers in order to achieve a systematic design methodology for reliable systems.

Abstract. We describe a new procedure of solving the electrostatic potentials in the silicon film of an undoped DG SOI MOSFET structure. Starting from a model previously described in the literature by Malobabic et al. (2004), we propose the bisection method for the solution of transcendental equation giving the surface electrostatic potential of the silicon channel, as a function of the gate to source voltage and the voltage along the channel. The above calculated results are used for obtaining the charges and corresponding drain current in the DG MOSFET transistor. The entire model is implemented in Verilog A and can be used inside Cadence for the determination of the static regime of electrical circuits based on undoped symmetric DG SOI MOSFET. As a case study, a simple common-source amplifier built with such a novel device is analyzed, showing the currents and voltages present in the circuit.

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