CONAN - A Design Exploration Framework for Reliable Nano-Electronics

Abstract

In this paper we introduce a design methodology that allows the system/circuit designer to build reliable systems out of unreliable nano-scale components. The central point of our approach is a generic (parametrical) architectural template, COnfigurable Nanostructures for reliAble Nano electronics (CONAN), which embeds support for reliability at various levels of abstractions. Some of the main reliability sources are regular and decentralized structures based on simple basic computation cells designed to be robust against disturbances and noise, fault tolerance based on hardware, time and information redundancy applied at the basic cell level as well as at higher levels, self diagnosis assisted by the dynamic reconfiguration of basic computation cells and interconnect rerouting. Within the CONAN template both technology dependent and independent models co-exists such that the more abstract layers are technology independent while the lower levels can be retargeted to various fabrication technologies. Our proposal is applicationoriented and allows the designers to deal with unpredictability, and low reliability, which are unavoidable characteristics of future emerging nano-devices. When combined with the underlying software, the tools supporting the CONAN approach allow the designer to check whether the design constraints are fulfilled before performing a detailed implementation and provides means to trade area, delay, and power consumptions for reliability. As such, this proposal is a call-to-arms to mobilize the efforts of systems designers in order to achieve a systematic design methodology for reliable systems.

Cell architecture for nanoelectronic design

“…It is very difficult to deal with all the problems arising in nanotechnology with a single level of circuits or tolerance strategy. As the origin of those problems is so different, it seems that tolerance mechanisms at several levels may be a better solution [11]. …”

Optimization of the Averaging Reliability Technique Using Low Redundancy Factors for Nanoscale Technologies

“…The optimal cluster size (N c,opt -also depicted in Fig. 12) for a given p f is derived from the expression dP module fails /dN c = 0, and is presented as The exact value of N c,opt cannot be obtained analytically in case of RMR (21). For P unit fails < 1%, the approximate analytical solution exists.…”

“…Solving the equation dP module fails /dR = 0 gives the minimal possible value for the probability of the module failure and redundancy factor that provides it. The numerical solution gives R, which substituted into (21) and (22) together with the condition P module fails < 0.1 reveals the maximal defect density that can be supported in order to achieve a yield Y > 0.9. Table IV shows the maximal tolerable defect density (p f ,max ) (maximal device probability of failure to achieve a yield over 90%) and the appropriate optimal redundancy factor (R opt ).…”

“…4) The size of fault-tolerant "islands"-reliable blocks to be inserted into the hardware must be reduced in comparison to currently applied techniques to adapt to new failure rates and densities as they occur in nanoscale technologies, where several defects may be expected to affect a relatively small area. 5) The application of only one of the fault-tolerant techniques will not be sufficient in order to tackle high defect densities; fault tolerance of future microelectronic circuit must be handled jointly at several levels of abstraction, e.g., at circuit level, architectural level, as well as at system level and algorithmic level; the massive nature of fault density will demand cooperative efforts from these various levels to absorb or recover from faults [21]. This paper presents solutions to some of the aforementioned issues, and supports the analysis of the averaging technique with theoretical developments, as well as application data.…”

Electronic System Design Paradigms in the Technologies of the Year 2020

“…This idea was first presented in [22]. Figure 11 shows an example of this strategy, where the different design flow levels (technology, transistors, circuit, gates, logic blocks…) are used to improve the reliability (the arbitrary numbers inside the column give idea of a continuous reduction of the error rate).…”