Implementation of Reed Solomon Encoder on Low-Latency Embedded FPGA in Flexible SoC based on ARM Processor

Saidi, Hajer; Turki, M.; Marrakchi, Zied; Obeid, Abdulfattah M.; Abid, Mohamed

doi:10.1109/iwcmc48107.2020.9148349

Cited by 6 publications

(5 citation statements)

References 10 publications

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“…This algorithm offers a new syndrome computation block with a view to minimize the number of iterations. The proposed corresponding circuit has been developed, synthesized, simulated, implemented on the FPGA card and compared to the existed one to demonstrate the difference between the two circuits and the number of reduced iterations, the comparison between circuits in table 1 proves that the RS code (15,11) has 256 iterations using the modified method while, 86 iterations using the basic method.…”

Section: Discussionmentioning

confidence: 99%

“…For the field GF [15][16]the corresponding primitive polynomial [17][18] is the following in the table 1 The minimum [19] RS code defines the number of symbols distance between two RS code words:…”

Section: Primitive Polynomialmentioning

confidence: 99%

“…The basic circuit of the syndrome computation block for RS (15,11) is expressed by the equation 4. S i = R(i) = r 14 (αi) 14 + r 13 (αi) 13 +r 1 (α i ) + r 0 (4)…”

Section: Case Of the Basic Circuitmentioning

confidence: 99%

“…The proposed algorithm has been implemented on a FPGA Card using Xilinx Spartan 3E-500 to verify the test setup which presented in figure 8. For the case of RS (15,11), we have four coefficients of syndrome Block (S0, S1, S2, S3). In Fig.…”

Section: Implementation Of Rs Codementioning

confidence: 99%

See 3 more Smart Citations

Development and Validation of an optimized syndromes block for reed solomon decoder

Mohamed,

Azeddine,

Anas El Habti

et al. 2023

ITM Web Conf.

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Reed Solomon decoder plays an indispensable role in many applications involving data transmission, storage applications and Video broadcasting DVB-T and DVB-S2. In this work we propose a new optimized parallel syndrome block [67] for the Reed Solomon RS code (15,11) used in digital Video broadcasting DVB-T. Therefore, this proposed parallel block is compared to the serial syndrome block existing. On the basis of this technique a new architecture based on three syndromes in parallel is developed. This technique reduces both the energy consumption and the number of iterations. The RS code (15, 11) is composed of 255 symbols that are multiples of 3. The symbols are entered in parallel in the syndrome block. These decoding algorithms developed in this work are compared with the existing algorithms, and they are evaluated through a simulation using the hardware description language VHDL, then they are implemented on a Xilinx Spartan type FPGA card using the XILINX software.

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Section: Discussionmentioning

confidence: 99%

Section: Primitive Polynomialmentioning

confidence: 99%

“…The basic circuit of the syndrome computation block for RS (15,11) is expressed by the equation 4. S i = R(i) = r 14 (αi) 14 + r 13 (αi) 13 +r 1 (α i ) + r 0 (4)…”

Section: Case Of the Basic Circuitmentioning

confidence: 99%

Section: Implementation Of Rs Codementioning

confidence: 99%

See 2 more Smart Citations

Development and Validation of an optimized syndromes block for reed solomon decoder

Mohamed,

Azeddine,

Anas El Habti

et al. 2023

ITM Web Conf.

View full text Add to dashboard Cite

show abstract

“…Particularly for the more demanding applications (low energy, high throughput, low latency), hardware implementations can be needed in order to better compete with other products in the market or just to meet requirements while achieving real-time compression of the data stream [11][12][13][14][15]. This tends to be particularly true for the encoder side, as in the case of remote sensing, like satellite applications or portable devices.…”

Section: Introductionmentioning

confidence: 99%

An FPGA-Based LOCO-ANS Implementation for Lossless and Near-Lossless Image Compression Using High-Level Synthesis

2021

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In this work, we present and evaluate a hardware architecture for the LOCO-ANS (Low Complexity Lossless Compression with Asymmetric Numeral Systems) lossless and near-lossless image compressor, which is based on JPEG-LS standard. The design is implemented in two FPGA generations, evaluating its performance for different codec configurations. The tests show that the design is capable of up to 40.5 MPixels/s and 124 MPixels/s per lane for Zynq 7020 and UltraScale+ FPGAs, respectively. Compared to the single thread LOCO-ANS software implementation running in a 1.2 GHz Raspberry Pi 3B, each hardware lane achieves 6.5 times higher throughput, even when implemented in an older and cost-optimized chip like the Zynq 7020. Results are also presented for a lossless only version, which achieves a lower footprint and approximately 50% higher performance than the version that supports both lossless and near-lossless. Interestingly, these great results were obtained applying High-Level Synthesis, describing the coder with C++ code, which tends to establish a trade-off between design time and quality of results. These results show that the algorithm is very suitable for hardware implementation. Moreover, the implemented system is faster and achieves higher compression than the best previously available near-lossless JPEG-LS hardware implementation.

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Development and Analysis of Novel Mesh of Tree-based embedded FPGA

Saidi

Turki²,

Marrakchi³

et al. 2022

J Supercomput

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Implementation of Reed Solomon Encoder on Low-Latency Embedded FPGA in Flexible SoC based on ARM Processor

Cited by 6 publications

References 10 publications

Development and Validation of an optimized syndromes block for reed solomon decoder

Development and Validation of an optimized syndromes block for reed solomon decoder

An FPGA-Based LOCO-ANS Implementation for Lossless and Near-Lossless Image Compression Using High-Level Synthesis

Development and Analysis of Novel Mesh of Tree-based embedded FPGA

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