2002 IEEE Nuclear Science Symposium Conference Record
DOI: 10.1109/nssmic.2002.1239373
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Implementation of the DTMROC-S ASIC for the ATLAS TRT detector in a 0.25 μm CMOS technology

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Cited by 4 publications
(5 citation statements)
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“…(b) a subsequent 16-channel ASIC fabricated in commercial radiation-tolerant 0.25µm CMOS technology [83]. This ASIC performs the drift-time measurement (∼ 3 ns binning).…”
Section: Trt Front-end Electronicsmentioning
confidence: 99%
“…(b) a subsequent 16-channel ASIC fabricated in commercial radiation-tolerant 0.25µm CMOS technology [83]. This ASIC performs the drift-time measurement (∼ 3 ns binning).…”
Section: Trt Front-end Electronicsmentioning
confidence: 99%
“…The implementation of design elements to eliminate radiation induced leakage currents (guard rings, enclosed layout transistors—ELTs) permitted the MOS devices to reach a very high level of radiation hardness [ 98 , 99 ]. Typical ASICs examples are DTMROC [ 100 , 101 ] and APV [ 102 , 103 ]. Starting from year 2000 the technology of choice for HEP applications was 0.25 μ m CMOS [ 104 107 ].…”
Section: Fast Readouts In Asic Prototypes For Scientific Applicatmentioning
confidence: 99%
“…SEU sensitivity was tested at the CERN PS irradiation facility using a 24 GeV proton beam with an integrated fluence of 1.8 × 10 14 p/cm 2 and shown to be of order 10 −14 cm 2 [8]. This rate of SEUs produces a per TRT error rate of much less than 1 Hz.…”
Section: Measured Performancementioning
confidence: 99%
“…Radiation tolerance was tested at the CEA Saclay Pagure facility up to 7 Mrad of Co 60 with the only degradation being about a 10% decrease in maximum DAC output voltage. SEU sensitivity was tested at the CERN PS irradiation facility using a 24 GeV proton beam with an integrated fluence of 1.8 × 10 14 p/cm 2 and shown to be of order 10 −14 cm 2 [8]. This rate of SEUs produces a per TRT error rate of much less than 1 Hz.…”
Section: Measured Performancementioning
confidence: 99%