Implementation of Wireless Communications Systems on FPGA-Based Platforms

Masselos, K.; Voros, Nikos S.

doi:10.1155/2007/12192

Cited by 5 publications

(2 citation statements)

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“…Due to the computational complexity of WLAN (Wireless local area network), and taking into account the capabilities of modern microprocessors, an implementation based exclusively on microprocessors is not convenient, requiring a large number of components. Parallel computation allows improving the efficiency of the implementation of the discrete components, and makes it possible to accelerate some complex parts of WLANs (Masselos & Voros, 2007). Of special interest results the benefits of FPGAs for embedded software radio devices.…”

Section: Fpga Applications In Communicationsmentioning

confidence: 99%

Design of Embedded Augmented Reality Systems

Toledo¹,

Martínez²,

Garrigós³

et al. 2010

Augmented Reality

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Section: Fpga Applications In Communicationsmentioning

confidence: 99%

Design of Embedded Augmented Reality Systems

Toledo¹,

Martínez²,

Garrigós³

et al. 2010

Augmented Reality

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“…The PDCCH architectures have computed the requirements that have several orders of magnitude greater than that of 3G CDMA based systems. The silicon technologies deployed in 4G systems will need to supply enormous computing capabilities (many hundreds of Gigaoperations/s), also require significant flexibility in order to support multi-mode base-station infrastructure equipment [6]. The second objective is to provide a complete FPGA implementation of transmitter/receiver architecture of LTE-advanced PDCCH for three different transmission techniques: (1) single input single output (SISO): 1 9 1; (2) multiple input multiple output (MIMO): 2 9 2, and (3) MIMO: 4 9 4, using two different FPGA kits, Xilinx Virtex-5 XC5VLX220T_FF1738 as well as Xilinx Spartan-6 XC6SLX45_2CSG324.…”

Section: Introductionmentioning

confidence: 99%

Fast Implementation of Different LTE Physical Downlink Control Channels Using FPGA

Mohamed

Abdel-Atty

Abou-El-Seoud

et al. 2015

Wireless Pers Commun

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Hardware implementation of LTE-advanced systems using FPGA technology is a highly promising technology for mobile communications and wireless networks researchers. The objective of this paper is to improve the processing speed; the system capabilities; the power consumption, and the processing delay of LTE-advanced downlink control channels due to the parallel processing nature of FPGA. Basically, the physical downlink control channel (PDCCH) is used to carry downlink control information (DCI). In which, an optimized HDL design for both transmitter and receiver of PDCCH will be presented. The design process of PDCCH transmitter and receiver are carried out in architecture under different antenna configurations including: single input single output: 1 9 1; multiple input multiple output (MIMO) 2 9 2, and MIMO 4 9 4. The complete LTE-advanced physical layer has been coded using VHDL as one of the most famous HDL languages. Designs have been synthesized using Xilinx Integrated Software Environment tool 14.2 on Xilinx Virtex-5 XC5VLX220T_FF1738 as well as Xilinx Spartan-6 XC6SLX45_2CSG324, the performance indices of these two FPGA kits, will be compared. To simulate the system on ModelSim SE 6.5, based on synthesize and implementation, in terms of register transfer level design, FPGA editor, and Xilinx Power Analyzer are discussed into an FPGA kit from the Xilinx vendor. As a result of the system implementation process, it was found that speed; number of registers and power consumption are improved. Finally, it is clear that the hardware is much faster than the software, as well as, reducing the power dissipation in Spartan-6 with respect to Vitex-5 FPGA configurations. KeywordsLong term evolution (LTE) Á Physical downlink control channel (PDCCH) Á Downlink control information (DCI) Á Multiple input multiple output (MIMO) Á Field programmable gate array (FPGA) Á Register transfer level (RTL) Abbreviations OFDM Orthogonal frequency division multiplexing SISO Single input single output MIMO Multiple input multiple output ISE Integrated simulation environment PHICH Physical hybrid indicator channel PCFICH Physical control format indicator channel VHDL Very high speed integrated circuits hardware description language

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VHDL Modeling of Wi-Fi MAC Layer for Transmitter

Bhavikatti

Kulkarni²

2009

2009 IEEE International Advance Computing Conference

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Implementation of Wireless Communications Systems on FPGA-Based Platforms

Cited by 5 publications

References 0 publications

Design of Embedded Augmented Reality Systems

Design of Embedded Augmented Reality Systems

Fast Implementation of Different LTE Physical Downlink Control Channels Using FPGA

VHDL Modeling of Wi-Fi MAC Layer for Transmitter

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