VHDL Modeling of Wi-Fi MAC Layer for Transmitter

Bhavikatti, A. M.; Kulkarni, Subhash

doi:10.1109/iadcc.2009.4808970

Cited by 5 publications

(1 citation statement)

References 1 publication

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“…Both languages (Verilog and VHDL) are directly tied to the simulator, it is easy to interact with the modeled device to get for example, valuable timing information and to gain unparalleled visibility into the internal state and signals, which is extremely useful during development and debug. Also, both languages provide built-in parameterization features for creating reusable components that designers can tailor to support different applications [18][19][20][21].…”

Section: Introductionmentioning

confidence: 99%

Verification Components Reuse

Sagahyroon¹,

Lakkaraj²,

Karunaratne³

2012

JCP

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Design verification of ASICs is often approached in an ad-hoc manner without the care, planning and scrutiny that usually accompanies a typical design effort. As the complexity of ASIC design increases, it is expected that the complexity of verification environments of such designs will increase as well. To reduce development time and effort, design reuse or the use of design blocks from one project to the next is often practiced. In this work, and in an effort to improve the efficiency of design verification efforts, we propose a methodology that advocates verification components reuse. The proposed approach utilizes a bottom-up, functional design verification strategy that encourages building and using modular and reusable verification components. The design of the hardware for the IEEE Ten Gigabit Ethernet standard is used to illustrate the feasibility and applicability of this approach.

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Section: Introductionmentioning

confidence: 99%