Implementation Study of Single Photon Avalanche Diodes (SPAD) in <formula formulatype="inline"><tex Notation="TeX">$0.8~\mu\hbox{m}$</tex> </formula> HV CMOS Technology

Abstract

Single Photon Avalanche Diodes (SPAD) are known for their excellent timing performance which enables Time of Flight capabilities in positron emission tomography (PET). However, current array architectures juxtapose the SPAD with its ancillary electronics at the expense of a poor fill factor of the SPAD array. The 3D vertical integration of SPADs and readout electronics represents a solution to the aforementioned problem. Compared to systems with external electronics readout, 3D vertical integration reduces the SPAD interconnect parasitic capacitance while greatly increasing the photosensitive area and improving overall performances. This paper presents the implementation of two SPAD structures designed for PET. The SPAD structures are designed using Teledyne DALSA high voltage (HV) CMOS technology targeted for a 3-dimensional single photon counting module (3DSPCM). SPAD with two types of guard ring (diffusion-based and virtual guard ring) are designed, fabricated and characterized. All structures are based on a anode in an -well cathode and are implemented along with active quenching circuits for proper characterization. The results show that the contact distribution and the anode-cathode spacing impact the dark count rate (DCR). The design of SPADs with a diffusion guard ring have a DCR down to s m at room temperature, afterpulsing probability of , timing resolution of 27 ps FWHM and PDE of 49% at 480 nm.

Quenching Circuit and SPAD Integrated in CMOS 65 nm with 7.8 ps FWHM Single Photon Timing Resolution

“…The SPAD is characterized using the methods presented in [30,45] with the test setup presented in Figure 7. The SPAD breakdown voltage was measured using IV curves.…”

Plug Silicon Photomultiplier for the & Imaging PET System: Physics, Technological Challenges and Application to Modern Nuclear Medicine

“…A possible implementation solution consists of designing diffusive guard rings, as shown on Figure 6. As an example such layout was developed using the Teledyne DALSA 800 nm HV and the BCDLITE GLOBALFOUNDRIES 180 nm CMOS processes [18,55]. Such layout is based on an inverted enclosure of the p + and nwell implantations, so that the high electric field zones at the edges of the diode are corrected with the geometrical distribution of the carriers.…”

“…The implementation of SiPM and SPAD sensitive cells in standard CMOS technology allows the combined integration of sensor and read-out electronics on the same device, with a significant reduction of power consumption and simplification of the operational conditions. In recent years a large number of advanced digital imagers and innovative concepts for light detection were proposed on this basis [15][16][17][18].…”

Review—The Mediating Effect of Chemically Oxidized Silicon Surface on the P4VP Electrografting for Silicon Electrical Insulation

“…13,14 Insulating TSV with P4VP is only possible if the grafted layer is thick enough to meet the dielectric requirement of the interconnection (dielectric constant and breakdown electric field). A strong dependence between the surface preparation of the sample and the final P4VP thickness exists.…”

“…8 So far, the compatibility of the P4VP electrografting process has been reported on high aspect ratio copper TSV, such as used for silicon interposers 7,8 and in Via-Last integration approach for 3D integration of a 22 × 22 photodiode array onto a CMOS control electronic ASIC. 13,14 Insulating TSV with P4VP is only possible if the grafted layer is thick enough to meet the dielectric requirement of the interconnection (dielectric constant and breakdown electric field). A strong dependence between the surface preparation of the sample and the final P4VP thickness exists.…”