Implementations of Reconfigurable Logic Arrays on FPGAs

Abstract

This paper presents a method to implement a reconfigurable logic array on an FPGA. To design circuits with 2-valued k-input LUTs, 2k-valued logic is introduced. Standard benchmark functions as well as symmetric functions are efficiently implemented by a logic array with 2k-valued variables. Number ofproducts and number of bits to represent functions by the expressions with 2k-valued variables for k = 1, 2, 3, 4, and 5 are compared. Both sumof-products expressions and EXOR sum-of-products expressions oJ 2k-valued logic significantly reduces needed FPGA resources, when 2 < k < 5. Experimental results for benchmark functions and symmetric functions are shown. Implementations of arrays with 16-valued variables on Xilinx and Altera FPGAs are also shown.

Memory-Efficient and Fast Run-Time Reconfiguration of Regularly Structured Designs

“…Therefore the truth table configuration bits can be changed by shifting in a new truth table. This idea is not novel and has been proposed various times in previous literature [3] [4] [5] [6].…”

A Fast Updatable Implementation of Index Generation Functions Using Multiple IGUs

“…For example, an index generation function can be represented by a registered vector table such as shown in Table 1. It can also be implemented by an FPGA [7], or a combination of memories and logic. Index generation functions are used in address tables in the Internet, terminal access controllers for local area networks, databases, memory patch circuits, dictionaries, password lists, etc.…”