Implementing a simple continuous speech recognition system on an FPGA

Melnikoff, Stephen J.; Quigley, Steven F.; Russell, Martin J.

doi:10.1109/fpga.2002.1106682

Cited by 32 publications

(12 citation statements)

References 4 publications

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“…Besides the resources, we also compared the power consumption of the two implementations, and also measured the performance. For our experiments, we considered 9 FIR filters of various sizes (6,10,13,20,28,41, 61, 119 and 151 tap filters). We targeted the Xilinx Virtex II device for our experiments.…”

Section: Methodsmentioning

confidence: 99%

FPGA Implementation of High Speed FIR Filters Using Add and Shift Method

Mirzaei

Hosangadi

Kastner

2006

2006 International Conference on Computer Design

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Abstract-We present a method for implementing high speed Finite Impulse Response (FIR) filters using just registered adders and hardwired shifts. We extensively use a modified common subexpression elimination algorithm to reduce the number of adders. We target our optimizations to Xilinx Virtex II devices where we compare our implementations with those produced by Xilinx CoregenTM using Distributed Arithmetic. We observe up to 50% reduction in the number of slices and up to 75% reduction in the number of LUTs for fully parallel implementations. We also observed up to 50% reduction in the total dynamic power consumption of the filters. Our designs perform significantly faster than the MAC filters, which use embedded multipliers.

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Section: Methodsmentioning

confidence: 99%

FPGA Implementation of High Speed FIR Filters Using Add and Shift Method

Mirzaei

Hosangadi

Kastner

2006

2006 International Conference on Computer Design

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“…Several studies have attempted to develop a speaker discrimination decoder from a narrow vocabulary using microcomputers and DSPs [4][5][6]. Other research has implemented these decoders using conventional statistical decoding [7,8]. In particular, a group transplanted HMM speech recognition to a microcomputer, which has completely semi-contentious distributions [9].…”

Section: Introductionmentioning

confidence: 99%

Frame-by-frame speech recognition as hardware decoding on FPGA devices

Nakayama

Shigekawa

Yokouchi

et al. 2015

2015 9th International Conference on Sensing Technology (ICST)

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This paper proposes frame-by-frame speech recognition as a hardware decoder on Field Programmable Gate Arrays (FPGAs). As a first step for FPGA implementation, Voice Activity Detection (VAD) using second order autocorrelation and a speech recognition decoder using formant frequency distances were evaluated. The hardware decoding was then implemented on an FPGA emulator. The VAD and decoder were demonstrated to be effective, and hence could be suitable for implementation on FPGA devices.

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“…Speech recognition became more popular due to the increased usage of digital-embedded systems like computers, mobile phones, cars, toys and other appliances [1]. These systems have to understand the Arabic language because, it is the second language in the world.The main idea is to convert voice signal to text by the computer in real-time manner, There are many algorithms to do such conversions.…”

Section: Introductionmentioning

confidence: 99%

Real-Time Arabic Speech Recognition

Mohammed¹,

Khidhir²

2013

IJCA

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Speech recognition system needs to perform a high complex calculation and short time to complete it. This is a big challenge for the real-time systems. However, using a simple and fast algorithm may do this task for the slow systems. Thus, the main objective of this paper is to design and implement a Real-Time Arabic Speech Recognition system using MATLAB environment. It is capable of accurately identifying some letters while remaining simple and fast. It uses the Mel-Frequency Cepstral Coefficients (MFCCs) as a feature extraction and Euclidean distance to compare the test sound and the database. A recognition rate of 89.6% has been reached.

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Implementing a simple continuous speech recognition system on an FPGA

Abstract: Abstract

Cited by 32 publications

References 4 publications

FPGA Implementation of High Speed FIR Filters Using Add and Shift Method

FPGA Implementation of High Speed FIR Filters Using Add and Shift Method

Frame-by-frame speech recognition as hardware decoding on FPGA devices

Real-Time Arabic Speech Recognition

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