Implementing and Analysing the Performance of Dadda Multiplier on FPGA

Abstract

Multiplication is an arithmetic operation where we will perform some arithmetic operations on the input operands and obtains the final result. Natural multiplication involves partial products generation and adding the obtained partial products to get the final result. But it consumes more power and time if the bit-width increases. Hence, we will use a Dadda Multiplier which results in increasing the execution speed and power efficiency and we will observe the same on FPGA. Hence this arithmetic technique can be used in various error tolerant applications such as image processing, digital processing and FFT.