Implementing digital finite impulse response filter using FPGA

Razak, Abdul; Zaharin, Muhamad Iqbal Abu; Haron, Nor Zaidi

doi:10.1109/apace.2007.4603854

Cited by 8 publications

(1 citation statement)

References 2 publications

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“…Razak et al [3] described the design of transposed form FIR filter on FPGAs using VHDL. Ab-Rahman et al [4] had presented ASIC design flow for the implementation of adaptive FIR filter using MATLAB and Mentor Graphics IC Design tools.…”

Section: Introductionmentioning

confidence: 99%

FPGA Implementation of Higher Order FIR Filter

Singh¹,

Prakash

2017

IJECE

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The digital Finite-Impulse-Response (FIR) filters are mainly employed in digital signal processing applications. The main components of digital FIR filters designed on FPGAs are the register bank to save the samples of signals, adder to implement sum operations and multiplier for multiplication of filter coefficients to signal samples. Although, design and implementation of digital FIR filters seem simple but the design bottleneck is multiplier block for speed, power consumption and FPGA chip area occupation. The multipliers are an integral part in FIR structures and these use a large part of the chip area. This limits the number of processing elements (PE) available on the chip to realize a higher order of filter. A model is developed in the Matlab/Simulink environment to investigate the performance of the desired higher order FIR filter. An equivalent FIR filter representation is designed by the Xilinx FIR Compiler by using the exported FIR filter coefficients. The Xilinx implementation flow is completed with the help of Xilinx ISE 14.5. It is observed how the use of higher order FIR filter impacts the resource utilization of the FPGA and it's the maximum operating frequency. Keyword:Fir filter FPGA Higher order fir filter Xilinx

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Section: Introductionmentioning

confidence: 99%