FPGA Implementation of Higher Order FIR Filter

Singh, Gurpadam; Prakash, Neelam Rup

doi:10.11591/ijece.v7i4.pp1874-1881

Cited by 12 publications

(3 citation statements)

References 18 publications

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“…The maximum frequency of the filter for the 8-bit word length is 57.3MHz, while the maximum frequency of the filter for the 12-bit and 16-bit word lengths is limited by the accumulation of reverse conversion results. The state-of-the-art comparison of proposed FIR design with other FPGA RNS FIR methods for three moduli set with a 32-bit unsigned input for a Xilinx Spartan 3E FPGA device has reduced 50% power dissipation and the frequency component is increased by 36.56% in proposed FSM decomposed RNS FIR design [30], [31]. Observation from Figure 3 can be made that the performance trade-off comparison for the conventional reverse computation of RNS with the proposed model, the filter tap extension with the logical elements were compared and the total performance loss is smaller when tested with possible higher-order during FIR filter design.…”

Section: Trade-off Analyzesmentioning

confidence: 98%

Low power residue number system using lookup table decomposition and finite state machine based post computation

Balaji

Nimmagadda²

2022

IJEECS

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In this paper, memory optimization and architectural level modifications are introduced for realizing the low power <span lang="EN-US">residue number system (RNS) with improved flexibility for electroencephalograph (EEG) signal classification. The proposed RNS framework is intended to maximize the reconfigurability of RNS for high-performance finite impulse response (FIR) filter design. By replacing the existing power-hungry RAM-based reverse conversion model with a highly decomposed lookup table (LUT) model which can produce the results without using any post accumulation process. The reverse conversion block is modified with an appropriate functional unit to accommodate FIR convolution results. The proposed approach is established to develop and execute pre-calculated inverters for various module sets. Therefore, the proposed LUT-decomposition with RNS multiplication-based post-accumulation technology provides a high-performance FIR filter architecture that allows different frequency response configuration elements. Experimental results shows the superior performance of decomposing LUT-based direct reverse conversion over other existing reverse conversion techniques adopted for energy-efficient RNS FIR implementations. When compared with the conventional RNS FIR design with the proposed FSM based decomposed RNS FIR, the logic elements (LEs) were reduced by 4.57%, the frequency component is increased by 31.79%, number of LUTs is reduced by 42.85%, and the power dissipation was reduced by 13.83%.</span>

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Section: Trade-off Analyzesmentioning

confidence: 98%

Low power residue number system using lookup table decomposition and finite state machine based post computation

Balaji

Nimmagadda²

2022

IJEECS

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“…So this design is only suitable for designs that require high performance that cannot be achieved through other approaches. The full custom design process is a considerable to solve problem in the engineering which are computational intensive [12].…”

Section: Full Custom Designmentioning

confidence: 99%

Design of Digital Parity Generator Layout Using 0.7 micron Technology

Musa¹,

Dali²,

Tolago³

2018

IJECE

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The proposed digital parity generator circuit is an integrated circuit functions to detect data errors at the transmitter end, and check it at the receiving end. In digital communications, the digital messages are transmitted in the form of 1’s and 0’s between two points. It is an error free if both are the same. The purpose of this research is to implement a design method of digital parity generator layout with 0.7 micron process technology ECPD07 from Tanner Tools. Layout design starts from making schematic circuit, test function and make a layout. Next, check the layout results in terms of design rules and verify the desired functionality gradually. The results show that the circuit has functioned well as an odd parity generator. The simulation results obtained with loads CL = 25 fF, tpLH = 2nS and tpHL = 1.46 nS indicate that tp = 1.73nS or operating frequency of 578 MHz. The integrated digital parity generator circuit using transmission gate has a size of 14758 um2 (78.5 um x188 um), consisting of 74 gates.<br /><br />

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“…Examples of hardware accelerators include multi-core CPU architectures, GPUs, application-specific integrated circuit ASICs, and FPGAs. Considering the cost, performance and energy consumption, the use of FPGAs in realtime applications is increasing [1][2]. FPGAs have been successfully employed in signal processing applications where both design flexibility and high performance are required.…”

Section: Introductionmentioning

confidence: 99%

FPGA Design of a High- Resolution FIR Band-Pass Filter by Using LabVIEW Environment

Tatar¹,

Bayar²,

Cicek³

2021

European Journal of Science and Technology

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Designers regularly use Finite Impulse Response (FIR) filters to fulfil the need for current electronic design applications such as signal or image processing and digital communications because of the remarkable selectivity computational efficiency. Fast and efficient information processing requires a dedicated microprocessor or a digital signal processor that may not always be available or provide enough performance. In such scenarios, designers can configure FPGAs for processing digitized signals. One of the most popular signal processing applications is filtering. Unlike the Infinite Impulse Response (IIR) filters, FIR filters do not have analog equivalent circuits. For this purpose, continuous time-discrete time conversion is not possible with the help of transforms. Because analog filters cannot have a finite impulse response, the design methods of FIR filters can be made as windowing method, pulse response truncation, and optimal filter design method. Considering this information, it aims to digitally separate two signals with different frequencies (2.4 kHz and 4.2 kHz), which are given to the input as analog, to obtain the desired information signal and suppress other signals. We preferred to use LabVIEW graphical programming language to get the digital FIR filter coefficients. We selected rectangular windowing, set the digital filter's sampling frequency as 18720 Hz, and determined the filter's coefficient with high-frequency resolution as 24. Using filter coefficients in the real-time FPGA-VHDL environment, we showed the performance and resource consumption. LabVIEW is used for simulation as well as obtaining filter coefficients. In addition, we compared both simulation and real-time FPGA-VHDL application output waveforms and examined both platforms' advantages and disadvantages.

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FPGA Implementation of Higher Order FIR Filter

Cited by 12 publications

References 18 publications

Low power residue number system using lookup table decomposition and finite state machine based post computation

Low power residue number system using lookup table decomposition and finite state machine based post computation

Design of Digital Parity Generator Layout Using 0.7 micron Technology

FPGA Design of a High- Resolution FIR Band-Pass Filter by Using LabVIEW Environment

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