Implementing Logic Functions Using Independently-Controlled Gate in Double-Gate Tunnel FETs: Investigation and Analysis

Abstract

Recently, a compact realization of logic gates using double-gate tunnel field effect transistors (DGTFETs) with independently-controlled gate has been proposed. The key elements in the proposed implementation are the suppression of the tunneling at the surface using gate-source overlap and enable tunneling inside the TFET body by choosing appropriate silicon body thickness. Though these implementations are compact, our study reveals that there are a few critical problems: high average subthreshold swing (SS avg), low ON-state current (I ON) and large propagation delay (t pd). In this paper, we examine the root cause of these problems and explore solutions to tackle them. It is demonstrated that the techniques that boost the I ON in a TFET do not necessarily increase the I ON /I OFF ratio in the proposed implementations. The efficacy of these techniques in improving the I ON /I OFF ratio depends on whether the gate-source overlap is able to suppress the tunneling at the surface and restrict the OFF-state current (I OFF). Furthermore, it is demonstrated that, for the AND functionality, compared to a purely silicon-based DGTFET (Si-TFET) employing silicongermanium heterojunction DGTFET (HJ-TFET) results in an increase in the I ON by 143×, an increase in the I ON /I OFF ratio by two orders of magnitude and an improvement in the SS avg by 45%, at V DD = 0.6 V. Moreover, a compact NAND gate realized using the proposed HJ-TFETs exhibits two orders of magnitude lower t pd , compared to the NAND gate realized using Si-TFET.

Realizing XOR and XNOR Functions Using Tunnel Field-Effect Transistors

“…The delays of the proposed devices are very high compared to the state-of-the-art CMOS circuits. This is expected since it is well known that Si-based TFET circuits exhibit higher delay due to low I ON and high C GD [5], [9], [10], [55], [59]. It is important to mention that this paper does not claim that the proposed realizations can outperform the state-of-the-art CMOS gates in terms of performance.…”

“…However, it is worth pointing out that in the proposed device, the I ON is low compared to the state-of-the-art MOSFETs. This is a known problem for Si-based TFETs [5], [10]. Furthermore, it is important to mention that in the proposed device, the tunneling current is dependent on the L gap , which is defined as the gap between the gates electrodes G 1 and G 2 .…”

“…We have calibrated the simulation model using [48]. The same tunneling model has been used in [9], [10], [15], [17], [46], [49]. Further, it is important to mention that the purpose of this work is to demonstrate how DGTFETs can be modified and employed in logic function realizations, rather than examining the exact current and voltage values.…”

“…Since the proposed implementations require fewer transistors than the CMOS-based implementation, it is expected that the proposed implementations are more compact and can reduce equivalent load capacitance. However, a more detailed study, accounting for the performance and energy-efficiency must be made to compare the proposed implementations with the CMOS-based implementations [9], [10].…”

“…Recently, certain logic functions have been proposed using a double-gate TFET (DGTFET). These implementations have been demonstrated to consume less area and reduce overall capacitance compared to the conventional CMOS-based implementations [9], [10].…”