Implementing self-aligned double patterning on non-gridded design layouts

Abstract

The Sidewall Spacer Double Patterning (SSDP) technique, also referred to as Self-Aligned Double Patterning (SADP), has been adopted as the primary double patterning solution for 32nm technology nodes and below for flash memory manufacturing. Many are now looking to migrate the technique to DRAM and random Logic layers. However, DRAM and especially Logic have far more complex layout requirements than NAND-FLASH, requiring a more sophisticated use of the SSDP technique. To handle the additional complexities an automated electronic design tool was used to calculate optimal layout splits of a design target into 2 or 3 masks. The model was programmed with immersion lithography and dry-193nm lithography MRC input rules and on wafer performance was tested. We discuss the patterning needs from the trim-mask and the pad-mask and associated lithography process window requirements and alignment accuracies necessary to pursue 32nm and 22nm half-pitch designs.

Self-aligned double patterning decomposition for overlay minimization and hot spot detection

“…[10] demonstrated an early work for 22nm logic cells with 1-D gridded design rules, but without the flexibility to handle the random 2-D patterns which are commonly seen in the logic design. [5] and [11] both demonstrated the initial idea of implementing SADP on 2D patterns with the core and trim mask design. [8] analyzed two main SADP processespositive tone process and negative tone process -and suggested the positive tone process would be preferred due to the large freedom of design and controllability over overlay.…”

Full area pattern decomposition of self-aligned double patterning for 30nm node NAND FLASH process

“…Among various DPT schemes, SADP has the advantage of excellent overlay performance in pitch splitting, and is therefore very useful for manufacturing devices with regular dense patterns, such as FLASH memory devices. Even though the nature of SADP restricts its freedom of 2-D or through-pitch pattern definition, recent studies [2,3] have demonstrated the capability of implementing SADP on both DRAM and logic layouts with the adoption of gridded or non-gridded design rule, as schematically shown in Figs.1 and 2. In SPIE 2009 [3], we had demonstrated the ideas of 30nm node NAND FLASH cell circuit critical feature definition by decomposing the target patterns to SADP defined dense array in conjunction with cropping and/or periphery masks steps, based on manual design.…”

Effective decomposition algorithm for self-aligned double patterning lithography

“…With the work in 2008, 9 SADP has shown the capability for the real implementation in the 22nm logic cells with 1-D gridded design rules, but without the flexibility to handle the random 2-D patterns which are commonly seen in the logic design, it was still far from a real application. Dai 10 and Sun 11 demonstrated the initial idea of implementing SADP on 2D patterns with the core and trim mask design. Ma 12 presented an important work which shows the analysis of the two main 2-D SADP processes -positive tone process and negative tone process.…”