Implementing Signatures for Transactional Memory

Sánchez,; Yen,; Hill,; Sankaralingam,

doi:10.1109/micro.2007.24

Cited by 95 publications

(79 citation statements)

References 32 publications

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“…Swarm's speculative execution borrows from LogTM and LogTM-SE [48,63,79]. Our key contributions over these and other speculation schemes are (i) conflict detection (Sec.…”

Section: Speculative Execution and Versioningmentioning

confidence: 99%

A scalable architecture for ordered parallelism

Jeffrey¹,

Subramanian²,

Yan³

et al. 2015

Proceedings of the 48th International Symposium on Microarchitecture

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We present Swarm, a novel architecture that exploits ordered irregular parallelism, which is abundant but hard to mine with current software and hardware techniques. In this architecture, programs consist of short tasks with programmer-specified timestamps. Swarm executes tasks speculatively and out of order, and efficiently speculates thousands of tasks ahead of the earliest active task to uncover ordered parallelism. Swarm builds on prior TLS and HTM schemes, and contributes several new techniques that allow it to scale to large core counts and speculation windows, including a new execution model, speculation-aware hardware task management, selective aborts, and scalable ordered commits.We evaluate Swarm on graph analytics, simulation, and database benchmarks. At 64 cores, Swarm achieves 51-122× speedups over a single-core system, and outperforms software-only parallel algorithms by 3-18×.

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“…Swarm's speculative execution borrows from LogTM and LogTM-SE [48,63,79]. Our key contributions over these and other speculation schemes are (i) conflict detection (Sec.…”

Section: Speculative Execution and Versioningmentioning

confidence: 99%

A scalable architecture for ordered parallelism

Jeffrey¹,

Subramanian²,

Yan³

et al. 2015

Proceedings of the 48th International Symposium on Microarchitecture

Self Cite

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“…Unless otherwise indicated, the sizes of the fields in a SigTable entry are those shown in Figure 8. To generate a signature, Pacman uses 8 128-bit Bloom filters in parallel using the H3 hash function from [25], for a total of 1,024 bits per signature.…”

Section: Methodsmentioning

confidence: 99%

Pacman: Tolerating asymmetric data races with unintrusive hardware

Otsuki

Nogueira

et al. 2012

IEEE International Symposium on High-Performance Comp Architecture

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Data races are a major contributor to parallel software unreliability. A type of race that is both common and typically harmful is the Asymmetric data race. It occurs when at least one of the racing threads is inside a critical section. Current proposals that target them are software-based. They slow down execution and require significant compiler, operating system (OS), or application changes.This paper proposes the first scheme to tolerate asymmetric data races in production runs with negligible execution overhead. The scheme, called Pacman, exploits cache coherence hardware to temporarily protect the variables that a thread accesses in a critical section from other threads' requests. Unlike previous schemes, Pacman induces negligible slowdown, needs no support from the compiler or (in the baseline design) from the OS, and requires no application source code changes. In addition, its hardware is relatively unintrusive. We test Pacman with the SPLASH-2, PARSEC, Sphinx3, and Apache codes, and discover two unreported asymmetric data races.

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“…An alternative approach to implement unbounded transactional memory is to use signatures [14,15,103,13,87]. Signatures are data structures that can store the access information, i.e., addresses and read-/write-sets, for a thread in a compact form using Bloom filters [7].…”

Section: Signature-based Transactional Memorymentioning

confidence: 99%

“…Various combinations of Bloom [7] and Cockoo hashing [73,74], called Cuckoo-Bloom Signatures have also been evaluated [87]. One filter encodes the read-set and one encodes the writeset.…”

Section: Signature-based Transactional Memorymentioning

confidence: 99%

Transactional memory

Grahn¹

2010

Journal of Parallel and Distributed Computing

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Current and future processor generations are based on multicore architectures where the performance increase comes from an increasing number of cores on a chip. In order to utilize the performance potential of multicore architectures the programs also need to be parallel, but writing parallel programs is a non-trivial task. Transactional memory tries to ease parallel program development by providing atomic and isolated execution of code sequences, enabling software composability and protected access to shared data. In addition, transactional memory has the ability to execute atomic code sequences in parallel as long as no data conflicts occur. Transactional memory implementation proposals exist for both hardware and software, as well as hybrid solutions. This special issue on transactional memory introduces transactional memory as a concept, presents an overview of some of the most important approaches so far, and finally, includes five articles that advances the state-of-the-art in transactional memory research.

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Implementing Signatures for Transactional Memory

Cited by 95 publications

References 32 publications

A scalable architecture for ordered parallelism

A scalable architecture for ordered parallelism

Pacman: Tolerating asymmetric data races with unintrusive hardware

Transactional memory

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