Implications of clock distribution faults and issues with screening them during manufacturing testing

Enhancing the Tolerance to Power-Supply Instability in Digital Circuits

“…To prevent this, a minimum-path length constraint should be added at the input of each CDC controlled flip-flop in the design. As done in other design solutions [6][8], these minimumpath constraints result in the addition of buffers during logic synthesis to slow down fast paths. The minimumpath constraint is equal to the clock edge trigger delay of the new CSL clock plus the propagation delay of the CSL block, i.e.,…”

“…Problems, such as crosstalk, overshoot / undershoot (momentarily signal rising / decreasing above/below the power supply voltage (V DD ) and ground (V SS ) lines) [2] [3], reflection, electromagnetic interference -EMI, signal skew (delay in arrival time to different receivers) [4] [5] and power-supply noise [3] can lead to functional errors, which may cause yield loss (at the production stage) and/or dependability loss (during product lifetime). Both the power grid and the clock distribution network need to be carefully designed and tested [6].…”

Can Clock Faults Be Detected Through Functional Test ?

“…We will show that clock faults, which we have in turn proven likely [13], can indeed give rise to min delay problems. We will then evaluate the probability that clock faults can be detected indirectly through functional testing.…”

“…As proven in [13], due to the vast routing (up and down the metal layers between buffering) and shielding of clocks (with V dd /V ss ), faults involving a clock signal (CK) are very likely. Particularly, this is the case of bridging faults (BFs) involving a clock net and V dd or V ss .…”

“…They can cause duty-cycle variations that may be neither detected through conventional structural testing, nor compensated by the existing calibration and correction schemes [13,14].…”