Implications of electronics constraints for solid-state quantum error correction and quantum circuit failure probability

Levy, James E.; Carroll, Malcolm S.; Ganti, Anand; Phillips, Cynthia A.; Landahl, Andrew J.; Gurrieri, Thomas M.; Carr, Robert D.; Stalford, Harold; Nielsen, Erik

doi:10.1088/1367-2630/13/8/083021

Cited by 13 publications

(18 citation statements)

References 33 publications

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“…Other work has studied quantum-computer architectures with only nearest-neighbor coupling between qubits in an array [30][31][32][33][34], which is appealing from a hardware design perspective. With the recent advances in the operation of the topological codes and their desirable characteristics such as having a high practical threshold and requiring only nearest-neighbor interactions, research effort has shifted toward architectures capable of building and maintaining large two-and three-dimensional cluster states [35][36][37][38].…”

Section: A Prior Work On Quantum-computer Architecturementioning

confidence: 99%

Layered Architecture for Quantum Computing

et al. 2012

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We develop a layered quantum-computer architecture, which is a systematic framework for tackling the individual challenges of developing a quantum computer while constructing a cohesive device design. We discuss many of the prominent techniques for implementing circuit-model quantum computing and introduce several new methods, with an emphasis on employing surface-code quantum error correction. In doing so, we propose a new quantum-computer architecture based on optical control of quantum dots. The time scales of physical-hardware operations and logical, error-corrected quantum gates differ by several orders of magnitude. By dividing functionality into layers, we can design and analyze subsystems independently, demonstrating the value of our layered architectural approach. Using this concrete hardware platform, we provide resource analysis for executing fault-tolerant quantum algorithms for integer factoring and quantum simulation, finding that the quantum-dot architecture we study could solve such problems on the time scale of days.

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Section: A Prior Work On Quantum-computer Architecturementioning

confidence: 99%

Layered Architecture for Quantum Computing

et al. 2012

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“…For instance, a 1-meter cable results in a round-trip time of ∼ 10 ns, which can be comparable to the duration of the quantum operations (Table 1). In order to limit the wiring complexity, two main approaches (or a combination of them) can be embraced [28,80]: multiplexing the control and read-out signals over a reduced set of wires (Section 5.2) and/or move the electronic interface closer to the qubits and operate it at cryogenic temperatures (Section 5.3).…”

Section: Challenges In Scaling-upmentioning

confidence: 99%

“…Additional electronics included with each switch enables the tuning of both the phase and amplitude so that the signals to each qubit can be individually calibrated to take into account qubit fabrication inhomogeneity. In order to further reduce the number of lines, the address can be sent over a serial interface [80].…”

Section: Multiplexing Solutionsmentioning

confidence: 99%

“…As a result, not only the execution of the quantum algorithm becomes longer, but also the qubits will be idle for extended periods of time during which decoherence takes place, as discussed in details in Ref. [80], thereby affecting the qubit fidelity. Furthermore, such multiplexing often requires a switch for each terminal of the quantum device.…”

Section: Multiplexing Solutionsmentioning

confidence: 99%

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The electronic interface for quantum processors

Dijk

Charbon

Foti

2019

Microprocessors and Microsystems

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Quantum computers can potentially provide an unprecedented speed-up with respect to traditional computers. However, a significant increase in the number of quantum bits (qubits) and their performance is required to demonstrate such quantum supremacy. While scaling up the underlying quantum processor is extremely challenging, building the electronics required to interface such large-scale processor is just as relevant and arduous. This paper discusses the challenges in designing a scalable electronic interface for quantum processors. To that end, we discuss the requirements dictated by different qubit technologies and present existing implementations of the electronic interface. The limitations in scaling up such state-of-the-art implementations are analyzed, and possible solutions to overcome those hurdles are reviewed. The benefits offered by operating the electronic interface at cryogenic temperatures in close proximity to the low-temperature qubits are discussed. Although several significant challenges must still be faced by researchers in the field of cryogenic control for quantum processors, a cryogenic electronic interface appears the viable solution to enable large-scale quantum computers able to address world-changing computational problems.

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“…[2]), we select physical units for the model that are relevant to double quantum dot (DQD) qubits to investigate the practical features of our results [20]. With this model system, we demonstrate that the DPC+OCT combination can be used to produce (a) improved fidelity compared to DPs alone and (b) improved robustness to uncertainty in the drift magnitude compared to results from DPs and OCT alone.…”

Section: Introductionmentioning

confidence: 99%

Optimized pulses for the control of uncertain qubits

et al. 2012

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Constructing high-fidelity control fields that are robust to control, system, and/or surrounding environment uncertainties is a crucial objective for quantum information processing. Using the two-state Landau-Zener model for illustrative simulations of a controlled qubit, we generate optimal controls for π/2-and π-pulses, and investigate their inherent robustness to uncertainty in the magnitude of the drift Hamiltonian.Next, we construct a quantum-control protocol to improve system-drift robustness by combining environment-decoupling pulse criteria and optimal control theory for unitary operations. By perturbatively expanding the unitary time-evolution operator for an open quantum system, previous analysis of environment-decoupling control pulses has calculated explicit control-field criteria to suppress environment-induced errors up to (but not including) third order from π/2-and π-pulses. We systematically integrate this criteria with optimal control theory, incorporating an estimate of the uncertain parameter, to produce improvements in gate fidelity and robustness, demonstrated via a numerical example based on double quantum dot qubits. For the qubit model used in this work, post facto analysis of the resulting controls suggests that realistic control-field fluctuations and noise may contribute just as significantly to gate errors as system and environment fluctuations.

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Implications of electronics constraints for solid-state quantum error correction and quantum circuit failure probability

Cited by 13 publications

References 33 publications

Layered Architecture for Quantum Computing

Layered Architecture for Quantum Computing

The electronic interface for quantum processors

Optimized pulses for the control of uncertain qubits

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