Implications of Imperfect Interfaces and Edges in Ultra-small MOSFET Characteristics

Abstract

PACS : 73.40.Qv; 85.30.De We use 3D statistical simulations to analyze the influence of imperfect interfaces and edges in sub-100 nm MOSFET characteristics. In particular, we focus on the impact of gates deformed by line edge roughness, and of oxide thickness variations resulting from a rough Si/SiO 2 interface. The 3D simulations are based on a very efficient 3D drift-diffusion framework, which can introduce quantum mechanical corrections via the density gradient formalism. Random features at the gate edges and at the Si/SiO 2 interface have similar statistical descriptions, but use different parameter sets in accordance with measurements. In MOSFETs, both line edge roughness and oxide thickness variations result in intrinsic parameter fluctuations, which are comparable in magnitude to random dopant effects. We simulate the dependence of intrinsic fluctuations on the statistical model parameters of the roughness. We also consider the scaling of devices with rough gate edges and rough SiO 2 interfaces. Our results highlight the importance of including realistic geometry features in the design and analysis of MOSFETs below 50 nm regime.

Statistical fluctuation of universal mobility curves in sub‐100 nm MOSFETs due to random oxide interface

“…The acceleration of the roadmap has drawn highlighted attention to intrinsic parameter fluctuations in MOSFETs, because they constitute one of the main 'showstoppers' for conventional CMOS scaling. Despite intrinsic fluctuations are often associated with discrete dopant charges [3], the atomicity of matter can also introduce substantial variations in the individual device characteristics [4]. The gate oxide thickness in 20 nm Intel devices [1], for example, is composed of only three silicon atomic layers.…”