A Statistical Model for Extracting Geometric Sources of Transistor Performance Variation

Ma, Siying; Keshavarzi, Ali; De, Vivek; Brews, J.R.

doi:10.1109/ted.2003.820648

Cited by 25 publications

(5 citation statements)

References 18 publications

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“…10 shows σ( Vth ) as a function of (LW) -1/2 . σ( Vth ) is almost proportional to (LW) -1/2 as reported in [3][4][5]. However some σ( Vth ) of MOSFETs with gate sizes are not on line in Fig.…”

Section: Measurements Results and Discussionsupporting

confidence: 54%

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A Test Structure for Statistical Evaluation of Characteristics Variability in a Very Large Number of MOSFETs

Watabe

Sugawa

Abe

et al. 2009

2009 IEEE International Conference on Microelectronic Test Structures

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We have proposed and developed a test structure for evaluating electrical characteristics variability of a large number of MOSFETs in very short time using very simple circuit structure.The electrical characteristics such as threshold voltage, subthreshold swings (S-factors, random telegraph signal noise, and so on, can be measured in over one million MOSFETs. This new test structure circuit and results measured by this circuit are very efficient in developing processes, process equipment and device structure which suppress variability.

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Section: Measurements Results and Discussionsupporting

confidence: 54%

“…Then, the gate size of current source transistors should be much larger than that of measured transistors to prevent the variability of I REF in each vertical line [3][4][5]. In this experiment, the gate size of current source is MOSFETs with W/L of 15 µm / 10 µm.…”

Section: Introductionmentioning

confidence: 99%

A Test Structure for Statistical Evaluation of Characteristics Variability in a Very Large Number of MOSFETs

Watabe

Sugawa

Abe

et al. 2009

2009 IEEE International Conference on Microelectronic Test Structures

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“…This simple model scales the relative statistical variation in delay, relative to the mean delay, using a power law. It is inspired by process parameter variation models such as the empirical threshold voltage variation model (Ma et al 2004) and Pelgrom model (Pelgrom 1989), which predict a decrease in device parameter variation with increasing device area, due to spatial averaging. The parameter γ gives the relative variation for a minimum sized gate (i.e., x i = 1), and the parameter α accounts for the space averaging effects of process and device parameter variations.…”

Section: Details Of the Statistical Circuit Sizing Examplementioning

confidence: 99%

A heuristic for optimizing stochastic activity networks with applications to statistical digital circuit sizing

et al. 2007

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A deterministic activity network (DAN) is a collection of activities, each with some duration, along with a set of precedence constraints, which specify that activities begin only when certain others have finished. One critical performance measure for an activity network is its makespan, which is the minimum time required to complete all activities. In a stochastic activity network (SAN), the durations of the activities and the makespan are random variables. The analysis of SANs is quite involved, but can be carried out numerically by Monte Carlo analysis.This paper concerns the optimization of a SAN, i.e., the choice of some design variables that affect the probability distributions of the activity durations. We concentrate on the problem of minimizing a quantile (e.g., 95%) of the makespan, subject to constraints on the variables. This problem has many applications, ranging from project management to digital integrated circuit (IC) sizing (the latter being our motivation). While there are effective methods for optimizing DANs, the SAN op-398 S.-J. Kim et al.timization problem is much more difficult; the few existing methods cannot handle large-scale problems.In this paper we introduce a heuristic method for approximately optimizing a SAN, by forming a related DAN optimization problem which includes extra margins in each of the activity durations to account for the variation. Since the method is based on optimizing a DAN, it readily handles large-scale problems. To assess the quality of the resulting suboptimal designs, we describe two widely applicable lower bounds on achievable performance in optimal SAN design.We demonstrate the method on a simplified statistical digital circuit sizing problem, in which the device widths affect both the mean and variance of the gate delays. Numerical experiments show that the resulting design is often substantially better than one in which the variation in delay is ignored, and is often quite close to the global optimum (as verified by the lower bounds).

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“…With these modifications, chip manufacturability and yield are improved but performance is adversely affected. There have been efforts to consider process variations such as gate CD, oxide thickness, metal width and thickness, temperature, voltage, etc., during circuit performance analysis at the design stage but this requires proper modeling of the variabilities [1, 2,3]. The most common approach to modeling variability, typically aimed at speed/frequency prediction, is based on "worst case scenarios" (corner cases).…”

Section: Introductionmentioning

confidence: 99%

Advanced timing analysis based on post-OPC extraction of critical dimensions

Yang

Capodieci

Sylvester

2005

Proceedings of the 42nd Annual Conference on Design Automation - DAC '05

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While performance specifications are verified before sign-off for a modern nanometer scale design, extensive application of optical proximity correction substantially alters the layout introducing systematic variations to the simulated and verified performance. As a result, actual on-silicon chip performance is quite different from sign-off expectations. This paper presents a new methodology to provide better estimates of on-silicon performance. The technique relies on the extraction of residual OPC errors from placed and routed full chip layouts to derive actual (i.e., calibrated to silicon) CD values that are then used in timing analysis and speed path characterization. This approach is applied to a state-of-theart microprocessor and contrasted with traditional design flow practices where ideal (i.e., drawn) Lgate values are employed, leading to a subsequent lack of predictive power. We present a platform for diagnosing and improving OPC quality on gates with specific functionality such as critical gates or matching transistors. Furthermore, with more accurate timing analysis we highlight the necessity of a post-OPC verification embedded design flow, by showing substantial differences in the Si-based timing simulations in terms of significant reordering of speed path criticality and a 36.4% increase in worst-case slack. Extensions of this methodology to multi-layer extraction and timing characterization are also proposed.

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A Statistical Model for Extracting Geometric Sources of Transistor Performance Variation

Cited by 25 publications

References 18 publications

A Test Structure for Statistical Evaluation of Characteristics Variability in a Very Large Number of MOSFETs

A Test Structure for Statistical Evaluation of Characteristics Variability in a Very Large Number of MOSFETs

A heuristic for optimizing stochastic activity networks with applications to statistical digital circuit sizing

Advanced timing analysis based on post-OPC extraction of critical dimensions

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