sampling clocksAbstract. This contribution deals with full digital modem architectures, and more specifically with multirate demodulators. We aim at an overall complexity minimization of the receiver structure, by implementing a completely asynchronous sampling scheme, in conjunction with a single optimized filtering module, which carries out the inter-symbol interference cancellation along with a specific interpolation algorithm. This allows to decrease the oversampling ratio down to the theoretical bound, thereby restraining computational requirements, while reducing dramatically the traditional analog circuitry. Concretely, such a multirate demodulator should ultimately appear as a low-cost AID converter operating at a unique sampling frequency, followed by an ASIC. A