Improved EPROM moisture performance using spin-on-glass (SOG) for passivation planarization

Gaeta, I.S.; Wu, K.

doi:10.1109/relphy.1989.36332

Cited by 3 publications

(1 citation statement)

References 2 publications

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“…SOG and BCB were chosen for planarization and bonding in VCSIT. SOG and BCB are widely used in the IC and MEMS industry as interlayer dielectric (ILD) [11], [18], passivation [22], [23], planarization [19], [20], and bonding materials [8], [21], because of their low dielectric constant, low-temperature process conditions and excellent chemical resistance. BCB is one of the preferred materials for biological applications since it has a very low moisture uptake (>0.2%) [10].…”

Section: Discussionmentioning

confidence: 99%

Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking

Uddin

Milaninia

Chen

et al. 2011

IEEE Trans. Compon., Packag. Manufact. Technol.

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This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.

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