For both n and pMOSFETs, this paper confirms via controlled wafer bending experiments and physical modeling the superiority of uniaxial over biaxial stressed Si and Ge MOSFETs. For uniaxial stressed p-MOSFETs, valence band warping creates favorable in and out-of-plane conductivity effective masses resulting in significantly larger hole mobility enhancement at low strain and high vertical field. For process-induced uniaxial stressed n-MOSFETs, a significant performance advantage results from a smaller threshold voltage shift due to less bandgap narrowing and the gate also being strained.
A novel mechanism for read disturb failures induced by FLASH EPROM cycling is reported. The mechanism causes unselected erased bits residing on selected wordlines to gain charge under low field conditions, causing them to appear programmed. It appears that this failure is due to electron tunneling barrier lowering by positive charge trapped during progrderase cycling. The Si-Si02 barrier in failing bits is reduced from 3.0 eV to under 1.0 eV at 70°C. The FLASH EPROM array failure rate dependence on cycling, stress voltage, temperature, and duty cycle i.s characterized. A low failure rate has been found for the fabrication process studied.
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