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This paper investigates the influence of the N-type buried layer (NBL) layout and LOCOS space on the ESD performance and trigger voltage of the lateral DMOS (LDMOS) device. Without adequate LOCOS spacing, LDMOS is vulnerable to ESD damage. If the LOCOS space is sufficiently wide, adding NBL structure can further improve LDMOS ESD performance significantly. This is because NBL can switch the current passage from the surface channel region to the bulk NBL during an ESD zapping, thus, avoiding localized highly damaging ESD current flow in the channel region.

In this letter, the dynamic turn-on mechanism of the n-MOSFET under high-current-stress event is investigated by using a real-time current and voltage measurement. Results reveal the existence of "self-consistent effect," i.e., the turn-on region of the parasitic n-p-n bipolar can change from one region to another region and increases with the stress current (I D ). Furthermore, experimental data show that the minimum substrate potential to sustain a stable snapback phenomenon is 0.9 V and increases with I D instead of 0.6-0.8 V and independent of I D as reported in early literatures.Index Terms-Avalanche breakdown, electrostatic discharge (ESD), high current, snapback.

The influence of the contact-to-contact space on the ESD performance of multi-finger silicided ground-gate NMOS (GGNMOS) is investigated. We find that the conventional contact layout, which has short contact-to-contact space, will induce current localization, and degrade the device ESD performance. Here we discuss how to design a ballast resistor for silicided multi-finger GGNMOS and show that lengthening the contact spacing can significantly improve device ESD performance (It2, HBM and MM). This improvement eliminates the short channel induced degradation of thin oxide device ESD.

A simple dynamic thermal model considering Joule-heating, heatconduction and energy conservation has been developed. It fits the dynamic thermal behavior of the silicided polysilicon under the high current stress event very well. The criterion to induce the DC resistance change of a silicided polysilicon resistor is determined by the phase transform temperature (PTT) of the silicide polysilicon.