Novel read disturb failure mechanism induced by FLASH cycling

Abstract

A novel mechanism for read disturb failures induced by FLASH EPROM cycling is reported. The mechanism causes unselected erased bits residing on selected wordlines to gain charge under low field conditions, causing them to appear programmed. It appears that this failure is due to electron tunneling barrier lowering by positive charge trapped during progrderase cycling. The Si-Si02 barrier in failing bits is reduced from 3.0 eV to under 1.0 eV at 70°C. The FLASH EPROM array failure rate dependence on cycling, stress voltage, temperature, and duty cycle i.s characterized. A low failure rate has been found for the fabrication process studied.

Radiation effects on floating-gate memory cells

“…These problems may increase with shrinking the cell size and the FG stored charge. Moreover, program/erase (P/E) cycles are well known to stress the tunnel oxide by producing local oxide defects [11], which can be enhanced by the ion-induced damage. Further, one of the peculiar reliability concerns of the FG memories resides in the threshold voltage distribution, which may show undesired overerased and overprogrammed tails external to the characteristic steep distribution in a Weibull plot [12].…”

Read disturb on flash memories: Study on temperature annealing effect

“…In literature [15], this model has been characterised and the Activation Energy calculated was very low ($0.2 eV). By the experimental trials we confirmed the validity of the model up to 85°C, while at 125°C we found a discrepancy between the data and the expected results.…”

Assessment of distributed-cycling schemes on 45nm NOR flash memory arrays

“…6, where the V T distributions of a 2bit/cell MLC technology are shown: during on-field operation, cell V T is compared against 3 read levels R1 -R3 but, in our experimental procedure, a WL stress higher than R3 is required to measure V T of cells belonging to L3. Thus, a careful investigation of the impact of stress field during V T acquisition is mandatory [33]- [37]. Disturbs arising from the V T map acquisition were evaluated by performing bake tests on fresh arrays, simply omitting the cycling phase in the experimental procedure depicted in Fig.…”