Improved Leakage and Reliability for ${\rm ZrLaO}_{x}/{\rm ZrTiO}_{x}/{\rm ZrLaO}_{x}$-Based MIM Capacitors by Plasma Nitridation

Lin, Chiu‐Chu; Wu, Yung-Hsien; Jiang, Ruo-Fan; Lin, Yubo; Yu, Menghan; Sun, Cherng-En

doi:10.1109/led.2013.2264748

Cited by 2 publications

(4 citation statements)

References 21 publications

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“…The reason of consecutive reading is to read the devices' resistance value more accurately and get the fluctuation from the resistance value of devices. [25] The voltage of the read operation is 0. Figure 2a shows the whole work process of our proposed framework, including training, predicting, and repair strategy.…”

Section: Endurance Prediction Model For Memory Arraymentioning

confidence: 99%

“…The initial pulses of the set operation are 1.3 V/700 ns applying on BL and reset operation 1.7 V/700 ns applying on WL, respectively, with the incremental step of 0.1 V. The voltage of the reading operation is 0.3 V. When the low resistance state (LRS) of the devices is lower than 30 KΩ within six steps, it is set success. [ 25 ] When the device's resistance value exceeds 200 KΩ in 6 steps, it is reset successfully. Figure S3 (Supporting Information) demonstrates the endurance characteristics of 1Kb cells on the 28 nm RRAM chip.…”

Section: Switching Mechanism and Reliability Issues In Memory Arraymentioning

confidence: 99%

“…The reason of consecutive reading is to read the devices’ resistance value more accurately and get the fluctuation from the resistance value of devices. [ 25 ] The voltage of the read operation is 0.3 V. The 100Read is comprised of 100Read HRS and 100Read LRS . Reading in HRS is named 100Read HRS , and reading in LRS is named 100Read LRS .…”

Section: Endurance Prediction Model For Memory Arraymentioning

confidence: 99%

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Lifetime Improvement of 28 nm Resistive Random Access Memory Chip by Machine Learning‐Assisted Prediction Model Collaborated with Resurrection Algorithm

Zheng,

Wu,

Xie

et al. 2024

Adv Elect Materials

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In this work, a machine learning‐assisted prediction model is proposed to analyze the reliability issues in the 28 nm resistive random access memory (RRAM) chip with raw data measured from RRAM test chip. The neural network of long‐short time memory (LSTM) is trained by the voltages and resistance during the endurance test (input vectors) and generates the output of the dichotomy states with a satisfied testing result >83.08%. According to the prediction results, the “real fail” state or “fake fail” state of the devices can get in the future. By collaborating with a well‐designed resurrection algorithm (RA), the percentage of real and fake failed cells dropped by 35% and 29%, respectively. Besides, the tail bits in retention significantly reduced from 33% to 14.6% due to the reduction of oxygen vacancies in the gaps of conducting filaments by applying ten consecutive cycles of RA. This intelligent prediction and repair module can prolong the lifetime of RRAM chips effectively in practical applications.

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Section: Endurance Prediction Model For Memory Arraymentioning

confidence: 99%

Section: Switching Mechanism and Reliability Issues In Memory Arraymentioning

confidence: 99%

Section: Endurance Prediction Model For Memory Arraymentioning

confidence: 99%

See 1 more Smart Citation

Lifetime Improvement of 28 nm Resistive Random Access Memory Chip by Machine Learning‐Assisted Prediction Model Collaborated with Resurrection Algorithm

Zheng,

Wu,

Xie

et al. 2024

Adv Elect Materials

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“…Incorporation of nitrogen into HK dielectrics by plasma process has been verified to be one of the most effective ways to passivate oxygen vacancies [10,11,12] and the mechanism is well supported by a sophisticated theory [8]. However, the plasma-based approach was commonly reported for planar devices and has been scarcely discussed in 3D FinFETs, and it may be due to the challenge to form conformal treatment of the tightly-pitched fins with high aspect ratio.…”

Section: Introductionmentioning

confidence: 99%

Enhanced sub 20-nm FinFET performance by stacked gate dielectric with less oxygen vacancies featuring higher current drive capability and superior reliability

Chen

Cho

Hsieh

et al. 2015

2015 IEEE International Electron Devices Meeting (IEDM)

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HK-2/HK-1 stacked dielectric was proposed as the gate dielectric for sub-20 nm FinFET technology. Compared to single HK-1 dielectric, the stacked gate dielectric exhibits superior performance in terms of improved drive current by 20~22% and increased transconductance by ~22%. The main reason accounting for the better performance, besides the higher gate capacitance by 4%, is the enhanced carrier mobility by ~33% resulting from less remote scattering due to smaller amount of charged oxygen vacancies which was physically confirmed by EELS and XPS. Owing to the reduced oxygen vacancies, from bias temperature instability and lifetime test, the stacked gate dielectric demonstrates augmented reliability as well. Most importantly, HK-1 and HK-2 are common dielectrics completely compatible with typical processes, rendering the stacked dielectric a promising one for next-generation FinFETs technology.

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Improved Leakage and Reliability for ${\rm ZrLaO}_{x}/{\rm ZrTiO}_{x}/{\rm ZrLaO}_{x}$-Based MIM Capacitors by Plasma Nitridation

Cited by 2 publications

References 21 publications

Lifetime Improvement of 28 nm Resistive Random Access Memory Chip by Machine Learning‐Assisted Prediction Model Collaborated with Resurrection Algorithm

Lifetime Improvement of 28 nm Resistive Random Access Memory Chip by Machine Learning‐Assisted Prediction Model Collaborated with Resurrection Algorithm

Enhanced sub 20-nm FinFET performance by stacked gate dielectric with less oxygen vacancies featuring higher current drive capability and superior reliability

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