Improved margin multi-class classification using dendritic neurons with morphological learning

Abstract

We present an architecture of a spike based multiclass classifier using neurons with non-linear dendrites and sparse synaptic connectivity where each synapse takes a binary value. The learning in this model happens not through weight updates but through structural changes, i.e. a change of connectivity between inputs and dendrites. Hence, it is well suited for implementation in neuromorphic systems using address event representation (AER). We present a new learning rule that allows better generalization of the system to noisy testing data making it feasible to transfer learnt weights in software to a hardware device interfacing with noisy spiking sensors. The new rule improves testing accuracy by 7 − 10% compared to earlier versions. We also present preliminary results for multi-class classification on handwritten digits from the MNIST database and show that our system can attain comparable performance (≈ 3% more error) with other reported spike based classifiers while using at least 50% less synaptic resources.

A current-mode spiking neural classifier with lumped dendritic nonlinearity

“…In [4], [6], the authors have suggested classifiers employing neurons with non-linear dendrites (NNLD) and binary synapses. Due to the presence of binary synapses, the learning in these type of architectures happen not by weight update but by morphological changes of the connections between inputs and dendrites.…”

“…Thus, these architectures are amenable for neuromorphic implementation employing AER protocols. We invite the reader to look into [4], [6] for a detailed description of the architectures and learning rules. In this paper, we present a circuit to implement the method proposed in [6] which has comparable performance as other spike based classifiers such as [7] but use 12X less synaptic resources.…”

“…In [6], the output of the two cell architecture was calculated by noting the difference of the output of the two NNLD:…”

“…For example, it is a heaviside function for classification. In [6], each of f + and f − are spike trains obtained from a spiking neuron and the comparison is done in a WTA. However, for our implementation, we found this has the problem of high common mode current at the input of the spiking neurons leading to frequency saturation.…”

“…Transistors M S2 , M S1 , M S3 and M S5 form a translinear loop. Hence, the current through M S5 is expressed as given in Equation 6. The transistor M S5 is biased to pass a maximum current of I sat (set by V BSAT ).…”