Improved Multimode TRL Calibration Method for Characterization of Homogeneous Differential Discontinuities

Liang, Wei; Quanli, Li; Wang, Zhengpeng; Wu, Jiamin

doi:10.1109/tim.2014.2351311

Cited by 17 publications

(4 citation statements)

References 21 publications

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“…The lower layer of the transmission line being tested is extended by 0.5 mm on both sides to ensure that the upper shielding does not obstruct the test pad. After the probe testing, the data is de-embedded to the actual reference surface using through-reflect-line (TRL) calibration method [16]. Fig.…”

Section: Test Methodsmentioning

confidence: 99%

Wafer Level 3D-stacked Integration Technology with Coplanar Hot via MMIC for mm-Wave Low-profile Applications

Zhu,

Zhou,

Zhou

2024

PIER Letters

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Wafer-level three-dimensional stacked integration technology is demonstrated in this paper, employing three gallium arsenide (GaAs) monolithic integrated circuits (MMICs) and gold (Au) bumps, and specifically designed for high-density and low-profile applications operating at millimeter-wave frequencies. A ground coplanar waveguide to ground coplanar waveguide (GCPW to GCPW) hot via interconnect has been developed to facilitate vertical transitions within a multi-stacked electromagnetic (EM) environment. Electrical connection between the upper and lower layers is achieved through 70 µm-height Au bumps. Compared to 2.5D packaging, this innovative structure exhibits an increased integration capability of more than three times within the same area, with a thickness of 0.451 mm. Ultra-wideband transmission between RF chips is achieved within a compact area of 0.16 square millimeters, enabling extremely shortdistance interconnect for system-in-package configurations. Appropriate utilization of ground metal within the package ensures strict electromagnetic field confinement, preventing interference from adjacent circuits. The designed transitions were fabricated and characterized. The measured result has an insertion loss of less than 0.65 dB and return loss of better than 20 dB up to 40 GHz for a back-to-back structure. This integration technology can further enhance integration capability, reduce transmission loss, and improve electromagnetic isolation. The presented approach holds significant potential for applications requiring high-density integration and reliable performance in the millimeter-wave regime.

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Section: Test Methodsmentioning

confidence: 99%

Wafer Level 3D-stacked Integration Technology with Coplanar Hot via MMIC for mm-Wave Low-profile Applications

Zhu,

Zhou,

Zhou

2024

PIER Letters

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“…TRL calibration methods should be specifically designed for different measurements. The automatic removal method of single port and double port fixture is also a de-embedding method [19]- [21]. The time domain reflectometry (TDR) method is used to measure the S parameters to reduce the number of measurements.…”

Section: Introductionmentioning

confidence: 99%

A Combination Method for Impedance Extraction of SMD Electronic Components Based on Full-Wave Simulation and De-Embedding Technique

XIAO,

ZHOU,

SHENG

et al. 2024

IEICE Trans. Fundamentals

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The method of extracting impedance parameters of surface mounted (SMD) electronic components by test is suitable for components with unknown model or material information, but requires consideration of errors caused by non-coaxial and measurement fixtures. In this paper, a fixture for impedance measurement is designed according to the characteristics of passive devices, and the fixture de-embedding method is used to eliminate errors and improve the test accuracy. The method of obtaining S parameters of fixture based on full wave simulation proposed in this paper can provide a thought for obtaining S parameters in deembedding. Taking a certain patch capacitor as an example, the S parameters for de-embedding were obtained using methods based on full wave simulation, 2×Thru, and ADS simulation, and de-embedding tests were conducted. The results indicate that obtaining the S parameter of the testing fixture based on full wave simulation and conducting de-embedding testing compared to ADS simulation can accurately extract the impedance parameters of SMD electronic components, which provides a reference for the study of electromagnetic interference (EMI) coupling mechanism.

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“…Regarding calibration, in [20], a multimode through-line-reflect (TRL) calibration based on generalized reverse cascade matrices was presented. In [21], multimode TRL calibration was applied for the characterization of homogeneous differential discontinuities.…”

Section: Introductionmentioning

confidence: 99%

Performance Evaluation of Broadband Characterization of Coupled Transmission Lines Even- and Odd-Mode Propagation Constants Using Differential and Common Mode S-Parameters

Pérez-Escribano¹,

Márquez-Segura²

2023

IEEE J. Microw.

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Improved Multimode TRL Calibration Method for Characterization of Homogeneous Differential Discontinuities

Cited by 17 publications

References 21 publications

Wafer Level 3D-stacked Integration Technology with Coplanar Hot via MMIC for mm-Wave Low-profile Applications

Wafer Level 3D-stacked Integration Technology with Coplanar Hot via MMIC for mm-Wave Low-profile Applications

A Combination Method for Impedance Extraction of SMD Electronic Components Based on Full-Wave Simulation and De-Embedding Technique

Performance Evaluation of Broadband Characterization of Coupled Transmission Lines Even- and Odd-Mode Propagation Constants Using Differential and Common Mode S-Parameters

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