The 10th IEEE International Symposium on Signal Processing and Information Technology 2010
DOI: 10.1109/isspit.2010.5711807
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Improved parameterized efficient FPGA implementations of parallel 1-D filtering algorithms using Xilinx System Generator

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Cited by 16 publications
(10 citation statements)
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“…In this paper, the authors have been presented a new SOA architecture proposal that comes from business analysis to SOA architectural design. The future work of this research is to implement the developed SOA in ASIC or FPGA hardware [11][12][13][14][15][16] for modern implications.…”
Section: Discussionmentioning
confidence: 99%
“…In this paper, the authors have been presented a new SOA architecture proposal that comes from business analysis to SOA architectural design. The future work of this research is to implement the developed SOA in ASIC or FPGA hardware [11][12][13][14][15][16] for modern implications.…”
Section: Discussionmentioning
confidence: 99%
“…The future enhancement of the system is by developing the security system of this work and implementing the developed system in ASIC or reconfigurable hardware [15][16][17][18][19][20]…”
Section: Future Workmentioning
confidence: 99%
“…He or she can also simulate its behavior using the same tools they would use in a standard Simulink project. This approach is widely used in various digital signal processing applications [15], [16]. However, the model still needs to be connected to other parts of the HDL project, which includes elements such as clock distribution, external memories, signal sources and sinks (also from and to other boards), ADCs, DACs, ets.…”
Section: Standard Simulink/system Generator Approachmentioning
confidence: 99%