Improved performance and reliability of split gate source-side injected flash memory cells

Bhattacharya, Shuvajit; Lai, Kang Wei; Fox, Kenneth; Chan, P.C.H.; Worley, E.; Sharma, Uma; Hwang, Liming; Li, G.P.

doi:10.1109/iedm.1996.553598

Cited by 12 publications

(4 citation statements)

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“…During these process steps, a sharp corner at the bottom edge of the AG encroaching under the FG in the vicinity of the gap region is formed. 19) These process issues cause the leakage between the FG and the AG in the split-gate flash memory, and studies of gap oxide technologies have been performed to prevent them. [19][20][21] In the proposed S4-NOR, it is possible to reduce L gap without suffering from the above-mentioned process issues in conventional split-gate structures, because both the AG and the FG are patterned simultaneously.…”

Section: Cell Structure and Process Technologymentioning

confidence: 99%

“…19) These process issues cause the leakage between the FG and the AG in the split-gate flash memory, and studies of gap oxide technologies have been performed to prevent them. [19][20][21] In the proposed S4-NOR, it is possible to reduce L gap without suffering from the above-mentioned process issues in conventional split-gate structures, because both the AG and the FG are patterned simultaneously. The key process steps for gap oxide formation in S4-NOR are shown in Fig.…”

Section: Cell Structure and Process Technologymentioning

confidence: 99%

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Source-side injection single-polysilicon split-gate flash memory

Yamauchi

Kamakura

Matsuoka

et al. 2014

Jpn. J. Appl. Phys.

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The source-side injection single-polysilicon split-gate NOR (S4-NOR) flash memory is proposed for embedded applications. For the S4-NOR cell, the access and floating gates are patterned on the channel between the source and drain junctions with a gap length of 55 nm using conventional photolithography technology, and the floating gate is capacitively coupled to an n-well memory gate. This technology can improve the compatibility with a single-polysilicon CMOS logic process. The memory cell is programmed within 5 µs with a low drain current of 10 µA, and its program efficiency is insensitive to process parameters except gap length, which are suitable for embedded memories from the process control viewpoint in addition to low power consumption. Good reliability is also realized without the effect of gap oxide leakage. Furthermore, the performance and reliability of the S4-NOR cell can be improved by scaling the logic process without using any special process.

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Section: Cell Structure and Process Technologymentioning

confidence: 99%

Section: Cell Structure and Process Technologymentioning

confidence: 99%

Source-side injection single-polysilicon split-gate flash memory

Yamauchi

Kamakura

Matsuoka

et al. 2014

Jpn. J. Appl. Phys.

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“…Flash [5][6][7][8] is a non-volatile and high packing dense memory technology. The typical structure is given in Fig.…”

Section: Fig 5 Schematic Cross-section Of a Flash-cellmentioning

confidence: 99%

Memory-Technologies: Pace-Setters for the IC-Industry

Klose

Dehm²,

Mueller³

et al. 2001

31st European Solid-State Device Research Conference

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“…[10][11][12][13][14] To meet its customized requirement, such as those for mobile or automotive application, the optimization of processes has been extensively discussed. [15][16][17][18][19][20][21][22][23][24][25] Recently, the development of the split gate has focused on a 3-poly structure, which has the advantages of low power and high coupling ratio. [25][26][27][28][29][30][31] By applying high voltage on an additional-assistance 3-poly gate, these sidewall split gate flashes can have a high coupling ratio and a low junction leakage as well.…”

Section: Introductionmentioning

confidence: 99%

A novel high-density embedded AND-type split gate flash memory

Shen

Wang

Pan

et al. 2014

Jpn. J. Appl. Phys.

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High-β spherical tokamak (ST) plasma conditions cut off propagation of electron cyclotron (EC) waves used for heating and current drive in conventional aspect ratio tokamaks. The electron Bernstein wave (EBW) has no density cutoff and is strongly absorbed and emitted at the EC harmonics, allowing EBWs to be used for heating and current drive in STs. However, this application requires efficient EBW coupling in the high-β, H-mode ST plasma regime. EBW emission (EBE) diagnostics and modelling have been employed on the National Spherical Torus Experiment (NSTX) to study oblique EBW to O-mode (B-X-O) coupling and propagation in H-mode plasmas. Efficient EBW coupling was measured before the L-H transition, but rapidly decayed thereafter. EBE simulations show that EBW collisional damping prior to mode conversion (MC) in the plasma scrape off reduces the coupling efficiency during the H-mode phase when the electron temperature is less than 30 eV inside the MC layer. Lithium evaporation during H-mode plasmas was successfully used to reduce this EBW collisional damping by reducing the electron density and increase the electron temperature in the plasma scrape off. Lithium conditioning increased the measured B-X-O coupling efficiency from less than 10% to 60%, consistent with EBE simulations.

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Improved performance and reliability of split gate source-side injected flash memory cells

Cited by 12 publications

References 0 publications

Source-side injection single-polysilicon split-gate flash memory

Source-side injection single-polysilicon split-gate flash memory

Memory-Technologies: Pace-Setters for the IC-Industry

A novel high-density embedded AND-type split gate flash memory

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